OrgACRN
/
acrn-hypervisor
mirror of https://github.com/projectacrn/acrn-hypervisor.git
1
0
Fork 0
Code Issues Releases Wiki Activity

dm: add default handling in pci_emul_capwrite 

Virtio 1.0 introduced several PCIY_VENDOR capabilities. When trying to
write to these capabilities no action is taken so the registers in
the capability of VIRTIO_PCI_CAP_PCI_CFG such as bar, offset and length
remain the default value 0. Later a read or write of pci_cfg_data needs
these information to perform the indirect read or write to the bar
region.

Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
This commit is contained in:
Jian Jun Chen 2018-05-18 13:25:25 +08:00 committed by lijinxia
parent f0729cd91d
commit b25a30f271
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
devicemodel/hw/pci/core.c
View File

@ -1086,6 +1086,7 @@ pci_emul_capwrite(struct pci_vdev *dev, int offset, int bytes, uint32_t val)
pciecap_cfgwrite(dev, capoff, offset, bytes, val); pciecap_cfgwrite(dev, capoff, offset, bytes, val);
break; break;
default: default:
CFGWRITE(dev, offset, val, bytes);
break; break;
} }
} }