HV: add whl-ipc-i5 configurations code in misc/vm_configs
Add whl-ipc-i5 configurations code in misc/vm_configs/ folder with new layout; Tracked-On: #5077 Signed-off-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Victor Sun
wenlingz
parent
62c87856ce
commit
b071cd6a67
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: American Megatrends Inc.
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* Version: WL10R104
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* Release Date: 09/12/2019
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* BIOS Revision: 5.13
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*
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* Base Board Information
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* Manufacturer: Maxtang
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* Product Name: WL10
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* Version: V1.0
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*/
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#include <board.h>
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#include <vtd.h>
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#include <msr.h>
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#include <pci.h>
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static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
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{
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.type = DRHD0_DEVSCOPE0_TYPE,
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.id = DRHD0_DEVSCOPE0_ID,
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.bus = DRHD0_DEVSCOPE0_BUS,
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.devfun = DRHD0_DEVSCOPE0_PATH,
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},
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};
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static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
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{
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.type = DRHD1_DEVSCOPE0_TYPE,
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.id = DRHD1_DEVSCOPE0_ID,
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.bus = DRHD1_DEVSCOPE0_BUS,
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.devfun = DRHD1_DEVSCOPE0_PATH,
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},
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{
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.type = DRHD1_DEVSCOPE1_TYPE,
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.id = DRHD1_DEVSCOPE1_ID,
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.bus = DRHD1_DEVSCOPE1_BUS,
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.devfun = DRHD1_DEVSCOPE1_PATH,
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},
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};
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static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
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{
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.dev_cnt = DRHD0_DEV_CNT,
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.segment = DRHD0_SEGMENT,
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.flags = DRHD0_FLAGS,
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.reg_base_addr = DRHD0_REG_BASE,
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.ignore = DRHD0_IGNORE,
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.devices = drhd0_dev_scope
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},
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{
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.dev_cnt = DRHD1_DEV_CNT,
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.segment = DRHD1_SEGMENT,
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.flags = DRHD1_FLAGS,
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.reg_base_addr = DRHD1_REG_BASE,
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.ignore = DRHD1_IGNORE,
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.devices = drhd1_dev_scope
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},
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};
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struct dmar_info plat_dmar_info = {
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.drhd_count = DRHD_COUNT,
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.drhd_units = drhd_info_array,
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};
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#ifdef CONFIG_RDT_ENABLED
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struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
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struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
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struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
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#endif
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static const struct cpu_cx_data board_cpu_cx[3] = {
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x33UL}, 0x02U, 0x97U, 0x00U}, /* C2 */
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x60UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */
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};
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static const struct cpu_px_data board_cpu_px[6] = {
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{0xBB9UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002700UL, 0x002700UL}, /* P0 */
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{0xBB8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001E00UL, 0x001E00UL}, /* P1 */
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{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P2 */
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{0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P3 */
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{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P4 */
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{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P5 */
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};
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const struct cpu_state_table board_cpu_state_tbl = {
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"Intel(R) Core(TM) i5-8265U CPU @ 1.60GHz",
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{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,
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(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
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};
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const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
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const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOARD_INFO_H
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#define BOARD_INFO_H
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#define MAX_PCPU_NUM 4U
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#define MAX_PLATFORM_CLOS_NUM 0U
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#define MAX_MBA_CLOS_NUM_ENTRIES 0U
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#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
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#define MAX_HIDDEN_PDEVS_NUM 0U
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#define HI_MMIO_START ~0UL
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#define HI_MMIO_END 0UL
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#define HI_MMIO_SIZE 0x0UL
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#endif /* BOARD_INFO_H */
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: American Megatrends Inc.
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* Version: WL10R104
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* Release Date: 09/12/2019
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* BIOS Revision: 5.13
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*
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* Base Board Information
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* Manufacturer: Maxtang
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* Product Name: WL10
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* Version: V1.0
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*/
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#ifndef PCI_DEVICES_H_
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#define PCI_DEVICES_H_
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#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
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#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}
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#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U}
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#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
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#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}
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#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}
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#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
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#define SD_HOST_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U}
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#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U}
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#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x04U}
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#define PCI_BRIDGE_2 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U}
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#define PCI_BRIDGE_3 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x01U}
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#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U}
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#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}
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#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}
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#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}
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#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U}
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#endif /* PCI_DEVICES_H_ */
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING!
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*/
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#ifndef PLATFORM_ACPI_INFO_H
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#define PLATFORM_ACPI_INFO_H
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/*
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* BIOS Information
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* Vendor: American Megatrends Inc.
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* Version: WL10R104
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* Release Date: 09/12/2019
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* BIOS Revision: 5.13
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*
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* Base Board Information
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* Manufacturer: Maxtang
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* Product Name: WL10
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* Version: V1.0
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*/
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/* pm sstate data */
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#define PM1A_EVT_ADDRESS 0x1800UL
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#define PM1A_EVT_ACCESS_SIZE 0x2U
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#define PM1A_CNT_ADDRESS 0x1804UL
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/* S3 is not supported by BIOS */
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#undef S3_PKG_VAL_PM1A
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#define S3_PKG_VAL_PM1A 0x0U
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#define WAKE_VECTOR_32 0x8C8AA08CUL
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#define WAKE_VECTOR_64 0x8C8AA098UL
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#define RESET_REGISTER_ADDRESS 0xCF9UL
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#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
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#define RESET_REGISTER_VALUE 0x6U
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/* DRHD of DMAR */
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#define DRHD_COUNT 2U
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#define DRHD0_DEV_CNT 0x1U
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#define DRHD0_SEGMENT 0x0U
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#define DRHD0_FLAGS 0x0U
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#define DRHD0_REG_BASE 0xFED90000UL
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#define DRHD0_IGNORE true
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#define DRHD0_DEVSCOPE0_TYPE 0x1U
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#define DRHD0_DEVSCOPE0_ID 0x0U
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#define DRHD0_DEVSCOPE0_BUS 0x0U
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#define DRHD0_DEVSCOPE0_PATH 0x10U
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#define DRHD1_DEV_CNT 0x2U
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#define DRHD1_SEGMENT 0x0U
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#define DRHD1_FLAGS 0x1U
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#define DRHD1_REG_BASE 0xFED91000UL
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#define DRHD1_IGNORE false
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#define DRHD1_DEVSCOPE0_TYPE 0x3U
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#define DRHD1_DEVSCOPE0_ID 0x2U
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#define DRHD1_DEVSCOPE0_BUS 0x0U
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#define DRHD1_DEVSCOPE0_PATH 0xf7U
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#define DRHD1_DEVSCOPE1_TYPE 0x4U
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#define DRHD1_DEVSCOPE1_ID 0x0U
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#define DRHD1_DEVSCOPE1_BUS 0x0U
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#define DRHD1_DEVSCOPE1_PATH 0xf6U
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/* PCI mmcfg base of MCFG */
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#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
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#endif /* PLATFORM_ACPI_INFO_H */
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#define SOS_ROOTFS "root=/dev/sda3 "
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#define SOS_CONSOLE "console=ttyS0 "
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#define SOS_COM1_BASE 0x3F8U
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#define SOS_COM1_IRQ 4U
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#define SOS_COM2_BASE 0x2F8U
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#define SOS_COM2_IRQ 3U
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#define SOS_BOOTARGS_DIFF "rw " \
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"rootwait " \
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"console=tty0 " \
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"consoleblank=0 " \
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"no_timer_check " \
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"quiet " \
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"loglevel=3 " \
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"i915.nuclear_pageflip=1 " \
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"hvlog=2M@0xe00000 " \
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"memmap=0x200000$0xe00000"
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#endif /* MISC_CFG_H */
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm_config.h>
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#include <pci_devices.h>
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#include <vpci.h>
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#include <vbar_base.h>
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#include <mmu.h>
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#include <page.h>
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VBAR_BASE_H_
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#define VBAR_BASE_H_
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#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xa0000000UL, \
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.vbar_base[2] = 0x90000000UL
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#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141e000UL
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#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1400000UL
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#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0xa1416000UL, \
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.vbar_base[2] = 0xa141d000UL
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#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141c000UL
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#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1414000UL, \
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.vbar_base[1] = 0xa141b000UL, \
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.vbar_base[5] = 0xa141a000UL
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#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1419000UL
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#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xa1410000UL, \
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.vbar_base[4] = 0xa1000000UL
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#define SMBUS_0_VBAR .vbar_base[0] = 0xa1418000UL
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#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0xfe010000UL
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#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1300000UL
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#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1200000UL, \
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.vbar_base[3] = 0xa1220000UL
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#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1100000UL, \
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.vbar_base[3] = 0xa1120000UL
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#endif /* VBAR_BASE_H_ */
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# Board defconfig generated by acrn-config tool
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CONFIG_BOARD="whl-ipc-i5"
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CONFIG_HV_RAM_START=0x11000000
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CONFIG_HV_RAM_SIZE=0x9600000
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CONFIG_PLATFORM_RAM_SIZE=0x400000000
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CONFIG_LOW_RAM_SIZE=0x00010000
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CONFIG_SOS_RAM_SIZE=0x400000000
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CONFIG_UOS_RAM_SIZE=0x200000000
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CONFIG_STACK_SIZE=0x2000
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CONFIG_GPU_SBDF=0x00000010
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CONFIG_UEFI_OS_LOADER_NAME=""
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CONFIG_SCHED_BVT=y
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CONFIG_RELOC=y
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CONFIG_MULTIBOOT2=y
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CONFIG_RDT_ENABLED=n
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CONFIG_CDP_ENABLED=n
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CONFIG_HYPERV_ENABLED=y
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CONFIG_IOMMU_ENFORCE_SNP=n
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CONFIG_ACPI_PARSE_ENABLED=y
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CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
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CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
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CONFIG_IOMMU_BUS_NUM=0x100
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CONFIG_MAX_IOAPIC_NUM=1
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CONFIG_MAX_IR_ENTRIES=256
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CONFIG_MAX_PCI_DEV_NUM=96
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CONFIG_MAX_IOAPIC_LINES=120
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CONFIG_MAX_PT_IRQ_ENTRIES=64
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CONFIG_MAX_MSIX_TABLE_NUM=64
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CONFIG_MAX_EMULATED_MMIO_REGIONS=16
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CONFIG_SERIAL_LEGACY=y
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CONFIG_SERIAL_PIO_BASE=0x3F8
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CONFIG_LOG_BUF_SIZE=0x40000
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CONFIG_NPK_LOGLEVEL_DEFAULT=5
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CONFIG_MEM_LOGLEVEL_DEFAULT=5
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CONFIG_LOG_DESTINATION=7
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CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3
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/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#define SOS_ROOTFS "root=/dev/sda3 "
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#define SOS_CONSOLE "console=ttyS0 "
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#define SOS_COM1_BASE 0x3F8U
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#define SOS_COM1_IRQ 4U
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#define SOS_COM2_BASE 0x2F8U
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#define SOS_COM2_IRQ 3U
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#define SOS_BOOTARGS_DIFF "rw " \
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"rootwait " \
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"console=tty0 " \
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"consoleblank=0 " \
|
||||
"no_timer_check " \
|
||||
"quiet " \
|
||||
"loglevel=3 " \
|
||||
"i915.nuclear_pageflip=1 " \
|
||||
"hvlog=2M@0xe00000 " \
|
||||
"memmap=0x200000$0xe00000"
|
||||
|
||||
#endif /* MISC_CFG_H */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
#include <pci_devices.h>
|
||||
#include <vpci.h>
|
||||
#include <vbar_base.h>
|
||||
#include <mmu.h>
|
||||
#include <page.h>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VBAR_BASE_H_
|
||||
#define VBAR_BASE_H_
|
||||
|
||||
#endif /* VBAR_BASE_H_ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# Board defconfig generated by acrn-config tool
|
||||
|
||||
CONFIG_BOARD="whl-ipc-i5"
|
||||
CONFIG_HV_RAM_START=0x11000000
|
||||
CONFIG_HV_RAM_SIZE=0x14800000
|
||||
CONFIG_PLATFORM_RAM_SIZE=0x400000000
|
||||
CONFIG_LOW_RAM_SIZE=0x00010000
|
||||
CONFIG_SOS_RAM_SIZE=0x400000000
|
||||
CONFIG_UOS_RAM_SIZE=0x200000000
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_GPU_SBDF=0x00000010
|
||||
CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi"
|
||||
CONFIG_SCHED_BVT=y
|
||||
CONFIG_RELOC=y
|
||||
CONFIG_MULTIBOOT2=y
|
||||
CONFIG_RDT_ENABLED=n
|
||||
CONFIG_CDP_ENABLED=n
|
||||
CONFIG_HYPERV_ENABLED=y
|
||||
CONFIG_IOMMU_ENFORCE_SNP=n
|
||||
CONFIG_ACPI_PARSE_ENABLED=y
|
||||
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
|
||||
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
|
||||
CONFIG_IOMMU_BUS_NUM=0x100
|
||||
CONFIG_MAX_IOAPIC_NUM=1
|
||||
CONFIG_MAX_IR_ENTRIES=256
|
||||
CONFIG_MAX_PCI_DEV_NUM=96
|
||||
CONFIG_MAX_IOAPIC_LINES=120
|
||||
CONFIG_MAX_PT_IRQ_ENTRIES=64
|
||||
CONFIG_MAX_MSIX_TABLE_NUM=64
|
||||
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
|
||||
CONFIG_SERIAL_LEGACY=y
|
||||
CONFIG_SERIAL_PIO_BASE=0x3F8
|
||||
CONFIG_LOG_BUF_SIZE=0x40000
|
||||
CONFIG_NPK_LOGLEVEL_DEFAULT=5
|
||||
CONFIG_MEM_LOGLEVEL_DEFAULT=5
|
||||
CONFIG_LOG_DESTINATION=7
|
||||
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MISC_CFG_H
|
||||
#define MISC_CFG_H
|
||||
|
||||
#endif /* MISC_CFG_H */
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
#include <pci_devices.h>
|
||||
#include <vpci.h>
|
||||
#include <vbar_base.h>
|
||||
#include <mmu.h>
|
||||
#include <page.h>
|
||||
|
||||
#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR
|
||||
|
||||
struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
|
||||
{
|
||||
.emu_type = PCI_DEV_TYPE_HVEMUL,
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
|
||||
.vdev_ops = &vhostbridge_ops,
|
||||
},
|
||||
{
|
||||
.emu_type = PCI_DEV_TYPE_PTDEV,
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
|
||||
PTDEV(SATA_CONTROLLER_0),
|
||||
},
|
||||
{
|
||||
.emu_type = PCI_DEV_TYPE_PTDEV,
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
|
||||
PTDEV(ETHERNET_CONTROLLER_0),
|
||||
},
|
||||
};
|
||||
|
||||
struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = {
|
||||
{
|
||||
.emu_type = PCI_DEV_TYPE_HVEMUL,
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
|
||||
.vdev_ops = &vhostbridge_ops,
|
||||
},
|
||||
{
|
||||
.emu_type = PCI_DEV_TYPE_PTDEV,
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
|
||||
PTDEV(USB_CONTROLLER_0),
|
||||
},
|
||||
{
|
||||
.emu_type = PCI_DEV_TYPE_PTDEV,
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
|
||||
PTDEV(ETHERNET_CONTROLLER_1),
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VBAR_BASE_H_
|
||||
#define VBAR_BASE_H_
|
||||
|
||||
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xa0000000UL, \
|
||||
.vbar_base[2] = 0x90000000UL
|
||||
|
||||
#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141e000UL
|
||||
|
||||
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1400000UL
|
||||
|
||||
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0xa1416000UL, \
|
||||
.vbar_base[2] = 0xa141d000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141c000UL
|
||||
|
||||
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1414000UL, \
|
||||
.vbar_base[1] = 0xa141b000UL, \
|
||||
.vbar_base[5] = 0xa141a000UL
|
||||
|
||||
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1419000UL
|
||||
|
||||
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xa1410000UL, \
|
||||
.vbar_base[4] = 0xa1000000UL
|
||||
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0xa1418000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0xfe010000UL
|
||||
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1300000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1200000UL, \
|
||||
.vbar_base[3] = 0xa1220000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1100000UL, \
|
||||
.vbar_base[3] = 0xa1120000UL
|
||||
|
||||
#endif /* VBAR_BASE_H_ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# Board defconfig generated by acrn-config tool
|
||||
|
||||
CONFIG_BOARD="whl-ipc-i5"
|
||||
CONFIG_HV_RAM_START=0x11000000
|
||||
CONFIG_HV_RAM_SIZE=0x7800000
|
||||
CONFIG_PLATFORM_RAM_SIZE=0x400000000
|
||||
CONFIG_LOW_RAM_SIZE=0x00010000
|
||||
CONFIG_SOS_RAM_SIZE=0x400000000
|
||||
CONFIG_UOS_RAM_SIZE=0x200000000
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_GPU_SBDF=0x00000010
|
||||
CONFIG_UEFI_OS_LOADER_NAME=""
|
||||
CONFIG_SCHED_BVT=y
|
||||
CONFIG_RELOC=y
|
||||
CONFIG_MULTIBOOT2=y
|
||||
CONFIG_RDT_ENABLED=n
|
||||
CONFIG_CDP_ENABLED=n
|
||||
CONFIG_HYPERV_ENABLED=y
|
||||
CONFIG_IOMMU_ENFORCE_SNP=n
|
||||
CONFIG_ACPI_PARSE_ENABLED=y
|
||||
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
|
||||
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
|
||||
CONFIG_IOMMU_BUS_NUM=0x100
|
||||
CONFIG_MAX_IOAPIC_NUM=1
|
||||
CONFIG_MAX_IR_ENTRIES=256
|
||||
CONFIG_MAX_PCI_DEV_NUM=96
|
||||
CONFIG_MAX_IOAPIC_LINES=120
|
||||
CONFIG_MAX_PT_IRQ_ENTRIES=64
|
||||
CONFIG_MAX_MSIX_TABLE_NUM=64
|
||||
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
|
||||
CONFIG_SERIAL_LEGACY=y
|
||||
CONFIG_SERIAL_PIO_BASE=0x3F8
|
||||
CONFIG_LOG_BUF_SIZE=0x40000
|
||||
CONFIG_NPK_LOGLEVEL_DEFAULT=5
|
||||
CONFIG_MEM_LOGLEVEL_DEFAULT=5
|
||||
CONFIG_LOG_DESTINATION=7
|
||||
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3
|
||||
Loading…
Reference in New Issue