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dm: Limit 64 bits PCI BAR region address space 

Limit 64 bits PCI BAR space from 0x100000000UL ~ 0x140000000UL,
as HV now only support 0x400000000UL+0x80000000 as top of guest memory
address. EPT table size is static allocated.

Tracked-On: #2577
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Shuo Liu 2019-01-29 17:48:17 +08:00 committed by wenlingz
parent 7628e790e7
commit aed75145c1
1 changed files with 2 additions and 2 deletions
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4
devicemodel/hw/pci/core.c
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@ -97,8 +97,8 @@ SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
#define PCI_EMUL_MEMBASE64 0x7000000000UL
#define PCI_EMUL_MEMLIMIT64 0x8D00000000UL
#define PCI_EMUL_MEMBASE64 0x100000000UL
#define PCI_EMUL_MEMLIMIT64 0x140000000UL
static struct pci_vdev_ops *pci_emul_finddev(char *name);
static void pci_lintr_route(struct pci_vdev *dev);