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acrn-config: generate proper msr_index value for CLOS 

Since msr_index relys on the MSR_IA32_L2_QOS_MASKn(n:max to 3)
macro which defined in hv source code, generate array that CLOS number
more than 4 means need define more than 4 macro.
This patch solve such issue by using MSR_IA32_L2/L3_MASK_BASE with the
msr index offset.

Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Wei Liu 2019-11-05 15:09:58 +08:00 committed by wenlingz
parent 6d9ff40183
commit ad9f424ce5
2 changed files with 26 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
misc/acrn-config/board_config/board_c.py
View File

@ -7,6 +7,17 @@ import sys
import board_cfg_lib
INCLUDE_HEADER = """
#include <board.h>
#include <vtd.h>"""
MSR_IA32_L2_MASK_BASE = 0x00000D10
MSR_IA32_L2_MASK_END = 0x00000D4F
MSR_IA32_L3_MASK_BASE = 0x00000C90
MSR_IA32_L3_MASK_END = 0x00000D0F
def gen_cat(config):
"""
Get CAT information
@ -15,34 +26,30 @@ def gen_cat(config):
err_dic = {}
(cache_support, clos_max) = board_cfg_lib.clos_info_parser(board_cfg_lib.BOARD_INFO_FILE)
print("\n#include <board.h>", file=config)
print("#include <acrn_common.h>", file=config)
print("#include <msr.h>", file=config)
if clos_max > MSR_IA32_L2_MASK_END - MSR_IA32_L2_MASK_BASE or\
clos_max > MSR_IA32_L3_MASK_END - MSR_IA32_L3_MASK_BASE:
err_dic["board config: generate board.c failed"] = "CLOS MAX should be less than reserved adress region length of L2/L3 cache"
return err_dic
if cache_support == "False" or clos_max == 0:
print("\nstruct platform_clos_info platform_clos_array[0];", file=config)
print("uint16_t platform_clos_num = 0;", file=config)
print("\nstruct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];", file=config)
else:
print("\nstruct platform_clos_info platform_clos_array[{0}] = {{".format(
clos_max), file=config)
print("\nstruct platform_clos_info platform_clos_array[{}] = {{".format(
"MAX_PLATFORM_CLOS_NUM"), file=config)
for i_cnt in range(clos_max):
print("\t{", file=config)
print("\t\t.clos_mask = {0},".format(hex(0xff)), file=config)
print("\t\t.clos_mask = {0}U,".format(hex(0xff)), file=config)
if cache_support == "L2":
print("\t\t.msr_index = MSR_IA32_{0}_MASK_{1},".format(
cache_support, i_cnt), file=config)
print("\t\t.msr_index = MSR_IA32_L2_MASK_BASE + {}U,".format(i_cnt), file=config)
elif cache_support == "L3":
print("\t\t.msr_index = {0}U,".format(hex(0x00000C90+i_cnt)), file=config)
print("\t\t.msr_index = MSR_IA32_L3_MASK_BASE + {}U,".format(i_cnt), file=config)
else:
err_dic['board config: generate board.c failed'] = "The input of {} was corrupted!".format(board_cfg_lib.BOARD_INFO_FILE)
return err_dic
print("\t},", file=config)
print("};\n", file=config)
print("uint16_t platform_clos_num = ", file=config, end="")
print("(uint16_t)(sizeof(platform_clos_array)/sizeof(struct platform_clos_info));",
file=config)
print("", file=config)
return err_dic
@ -92,6 +99,7 @@ def generate_file(config):
# insert bios info into board.c
board_cfg_lib.handle_bios_info(config)
print(INCLUDE_HEADER, file=config)
# start to parser to get CAT info
err_dic = gen_cat(config)

4
misc/acrn-config/board_config/misc_cfg_h.py
View File

@ -124,6 +124,10 @@ def generate_file(config):
# define CONFIG_MAX_PCPCU_NUM
print("#define CONFIG_MAX_PCPU_NUM\t{}U".format(max_cpu_num), file=config)
# set macro of max clos number
(cache_support, clos_max) = board_cfg_lib.clos_info_parser(board_cfg_lib.BOARD_INFO_FILE)
print("#define MAX_PLATFORM_CLOS_NUM\t{}U".format(clos_max), file=config)
# define rootfs with macro
for i in range(root_dev_num):
print('#define ROOTFS_{}\t\t"root={} "'.format(i, root_devs[i]), file=config)