hv: cpu_context is not only used by guest.
It could be also used by host as well. So we remove GUEST from MACRO name Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Eddie Dong <Eddie.dong@intel.com>
This commit is contained in:
parent
1d66aaacf3
commit
ad59375dfd
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@ -376,55 +376,55 @@ void bsp_boot_init(void)
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ASSERT(NR_WORLD == 2, "Only 2 Worlds supported!");
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ASSERT(offsetof(struct cpu_regs, rax) ==
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VMX_MACHINE_T_GUEST_RAX_OFFSET,
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CPU_CONTEXT_OFFSET_RAX,
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"cpu_regs rax offset not match");
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ASSERT(offsetof(struct cpu_regs, rbx) ==
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VMX_MACHINE_T_GUEST_RBX_OFFSET,
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CPU_CONTEXT_OFFSET_RBX,
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"cpu_regs rbx offset not match");
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ASSERT(offsetof(struct cpu_regs, rcx) ==
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VMX_MACHINE_T_GUEST_RCX_OFFSET,
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CPU_CONTEXT_OFFSET_RCX,
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"cpu_regs rcx offset not match");
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ASSERT(offsetof(struct cpu_regs, rdx) ==
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VMX_MACHINE_T_GUEST_RDX_OFFSET,
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CPU_CONTEXT_OFFSET_RDX,
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"cpu_regs rdx offset not match");
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ASSERT(offsetof(struct cpu_regs, rbp) ==
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VMX_MACHINE_T_GUEST_RBP_OFFSET,
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CPU_CONTEXT_OFFSET_RBP,
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"cpu_regs rbp offset not match");
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ASSERT(offsetof(struct cpu_regs, rsi) ==
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VMX_MACHINE_T_GUEST_RSI_OFFSET,
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CPU_CONTEXT_OFFSET_RSI,
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"cpu_regs rsi offset not match");
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ASSERT(offsetof(struct cpu_regs, rdi) ==
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VMX_MACHINE_T_GUEST_RDI_OFFSET,
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CPU_CONTEXT_OFFSET_RDI,
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"cpu_regs rdi offset not match");
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ASSERT(offsetof(struct cpu_regs, r8) ==
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VMX_MACHINE_T_GUEST_R8_OFFSET,
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CPU_CONTEXT_OFFSET_R8,
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"cpu_regs r8 offset not match");
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ASSERT(offsetof(struct cpu_regs, r9) ==
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VMX_MACHINE_T_GUEST_R9_OFFSET,
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CPU_CONTEXT_OFFSET_R9,
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"cpu_regs r9 offset not match");
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ASSERT(offsetof(struct cpu_regs, r10) ==
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VMX_MACHINE_T_GUEST_R10_OFFSET,
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CPU_CONTEXT_OFFSET_R10,
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"cpu_regs r10 offset not match");
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ASSERT(offsetof(struct cpu_regs, r11) ==
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VMX_MACHINE_T_GUEST_R11_OFFSET,
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CPU_CONTEXT_OFFSET_R11,
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"cpu_regs r11 offset not match");
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ASSERT(offsetof(struct cpu_regs, r12) ==
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VMX_MACHINE_T_GUEST_R12_OFFSET,
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CPU_CONTEXT_OFFSET_R12,
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"cpu_regs r12 offset not match");
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ASSERT(offsetof(struct cpu_regs, r13) ==
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VMX_MACHINE_T_GUEST_R13_OFFSET,
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CPU_CONTEXT_OFFSET_R13,
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"cpu_regs r13 offset not match");
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ASSERT(offsetof(struct cpu_regs, r14) ==
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VMX_MACHINE_T_GUEST_R14_OFFSET,
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CPU_CONTEXT_OFFSET_R14,
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"cpu_regs r14 offset not match");
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ASSERT(offsetof(struct cpu_regs, r15) ==
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VMX_MACHINE_T_GUEST_R15_OFFSET,
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CPU_CONTEXT_OFFSET_R15,
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"cpu_regs r15 offset not match");
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ASSERT(offsetof(struct run_context, cr2) ==
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VMX_MACHINE_T_GUEST_CR2_OFFSET,
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CPU_CONTEXT_OFFSET_CR2,
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"run_context cr2 offset not match");
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ASSERT(offsetof(struct run_context, ia32_spec_ctrl) ==
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VMX_MACHINE_T_GUEST_SPEC_CTRL_OFFSET,
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CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL,
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"run_context ia32_spec_ctrl offset not match");
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__bitmap_set(CPU_BOOT_ID, &pcpu_active_bitmap);
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@ -240,22 +240,22 @@ int cr_access_vmexit_handler(struct vcpu *vcpu)
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struct run_context *cur_context =
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&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
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static const int reg_trans_tab[] = {
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[0] = VMX_MACHINE_T_GUEST_RAX_INDEX,
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[1] = VMX_MACHINE_T_GUEST_RCX_INDEX,
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[2] = VMX_MACHINE_T_GUEST_RDX_INDEX,
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[3] = VMX_MACHINE_T_GUEST_RBX_INDEX,
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[0] = CPU_CONTEXT_INDEX_RAX,
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[1] = CPU_CONTEXT_INDEX_RCX,
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[2] = CPU_CONTEXT_INDEX_RDX,
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[3] = CPU_CONTEXT_INDEX_RBX,
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[4] = 0xFF, /* for sp reg, should not be used, just for init */
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[5] = VMX_MACHINE_T_GUEST_RBP_INDEX,
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[6] = VMX_MACHINE_T_GUEST_RSI_INDEX,
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[7] = VMX_MACHINE_T_GUEST_RDI_INDEX,
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[8] = VMX_MACHINE_T_GUEST_R8_INDEX,
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[9] = VMX_MACHINE_T_GUEST_R9_INDEX,
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[10] = VMX_MACHINE_T_GUEST_R10_INDEX,
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[11] = VMX_MACHINE_T_GUEST_R11_INDEX,
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[12] = VMX_MACHINE_T_GUEST_R12_INDEX,
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[13] = VMX_MACHINE_T_GUEST_R13_INDEX,
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[14] = VMX_MACHINE_T_GUEST_R14_INDEX,
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[15] = VMX_MACHINE_T_GUEST_R15_INDEX
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[5] = CPU_CONTEXT_INDEX_RBP,
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[6] = CPU_CONTEXT_INDEX_RSI,
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[7] = CPU_CONTEXT_INDEX_RDI,
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[8] = CPU_CONTEXT_INDEX_R8,
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[9] = CPU_CONTEXT_INDEX_R9,
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[10] = CPU_CONTEXT_INDEX_R10,
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[11] = CPU_CONTEXT_INDEX_R11,
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[12] = CPU_CONTEXT_INDEX_R12,
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[13] = CPU_CONTEXT_INDEX_R13,
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[14] = CPU_CONTEXT_INDEX_R14,
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[15] = CPU_CONTEXT_INDEX_R15,
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};
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int idx = VM_EXIT_CR_ACCESS_REG_IDX(vcpu->arch_vcpu.exit_qualification);
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@ -59,7 +59,7 @@ vmx_vmrun:
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/* 0x00000048 = MSR_IA32_SPEC_CTRL */
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movl $0x00000048,%ecx
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mov VMX_MACHINE_T_GUEST_SPEC_CTRL_OFFSET(%rdi),%rax
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mov CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rdi),%rax
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movl $0,%edx
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wrmsr
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@ -80,25 +80,25 @@ next:
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/* Compare the launch flag to see if launching (1) or resuming (0) */
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cmp $VM_LAUNCH, %rsi
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mov VMX_MACHINE_T_GUEST_CR2_OFFSET(%rdi),%rax
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mov CPU_CONTEXT_OFFSET_CR2(%rdi),%rax
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mov %rax,%cr2
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mov VMX_MACHINE_T_GUEST_RAX_OFFSET(%rdi),%rax
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mov VMX_MACHINE_T_GUEST_RBX_OFFSET(%rdi),%rbx
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mov VMX_MACHINE_T_GUEST_RCX_OFFSET(%rdi),%rcx
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mov VMX_MACHINE_T_GUEST_RDX_OFFSET(%rdi),%rdx
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mov VMX_MACHINE_T_GUEST_RBP_OFFSET(%rdi),%rbp
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mov VMX_MACHINE_T_GUEST_RSI_OFFSET(%rdi),%rsi
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mov VMX_MACHINE_T_GUEST_R8_OFFSET(%rdi),%r8
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mov VMX_MACHINE_T_GUEST_R9_OFFSET(%rdi),%r9
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mov VMX_MACHINE_T_GUEST_R10_OFFSET(%rdi),%r10
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mov VMX_MACHINE_T_GUEST_R11_OFFSET(%rdi),%r11
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mov VMX_MACHINE_T_GUEST_R12_OFFSET(%rdi),%r12
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mov VMX_MACHINE_T_GUEST_R13_OFFSET(%rdi),%r13
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mov VMX_MACHINE_T_GUEST_R14_OFFSET(%rdi),%r14
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mov VMX_MACHINE_T_GUEST_R15_OFFSET(%rdi),%r15
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mov CPU_CONTEXT_OFFSET_RAX(%rdi),%rax
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mov CPU_CONTEXT_OFFSET_RBX(%rdi),%rbx
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mov CPU_CONTEXT_OFFSET_RCX(%rdi),%rcx
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mov CPU_CONTEXT_OFFSET_RDX(%rdi),%rdx
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mov CPU_CONTEXT_OFFSET_RBP(%rdi),%rbp
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mov CPU_CONTEXT_OFFSET_RSI(%rdi),%rsi
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mov CPU_CONTEXT_OFFSET_R8(%rdi),%r8
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mov CPU_CONTEXT_OFFSET_R9(%rdi),%r9
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mov CPU_CONTEXT_OFFSET_R10(%rdi),%r10
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mov CPU_CONTEXT_OFFSET_R11(%rdi),%r11
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mov CPU_CONTEXT_OFFSET_R12(%rdi),%r12
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mov CPU_CONTEXT_OFFSET_R13(%rdi),%r13
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mov CPU_CONTEXT_OFFSET_R14(%rdi),%r14
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mov CPU_CONTEXT_OFFSET_R15(%rdi),%r15
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mov VMX_MACHINE_T_GUEST_RDI_OFFSET(%rdi),%rdi
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mov CPU_CONTEXT_OFFSET_RDI(%rdi),%rdi
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/* Execute appropriate VMX instruction */
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je vm_launch
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@ -122,30 +122,30 @@ vm_exit:
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xchg 0(%rsp),%rdi
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/* Save current GPRs to guest state area */
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mov %rax,VMX_MACHINE_T_GUEST_RAX_OFFSET(%rdi)
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mov %rax,CPU_CONTEXT_OFFSET_RAX(%rdi)
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mov %cr2,%rax
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mov %rax,VMX_MACHINE_T_GUEST_CR2_OFFSET(%rdi)
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mov %rax,CPU_CONTEXT_OFFSET_CR2(%rdi)
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mov %rbx,VMX_MACHINE_T_GUEST_RBX_OFFSET(%rdi)
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mov %rcx,VMX_MACHINE_T_GUEST_RCX_OFFSET(%rdi)
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mov %rdx,VMX_MACHINE_T_GUEST_RDX_OFFSET(%rdi)
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mov %rbp,VMX_MACHINE_T_GUEST_RBP_OFFSET(%rdi)
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mov %rsi,VMX_MACHINE_T_GUEST_RSI_OFFSET(%rdi)
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mov %r8,VMX_MACHINE_T_GUEST_R8_OFFSET(%rdi)
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mov %r9,VMX_MACHINE_T_GUEST_R9_OFFSET(%rdi)
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mov %r10,VMX_MACHINE_T_GUEST_R10_OFFSET(%rdi)
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mov %r11,VMX_MACHINE_T_GUEST_R11_OFFSET(%rdi)
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mov %r12,VMX_MACHINE_T_GUEST_R12_OFFSET(%rdi)
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mov %r13,VMX_MACHINE_T_GUEST_R13_OFFSET(%rdi)
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mov %r14,VMX_MACHINE_T_GUEST_R14_OFFSET(%rdi)
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mov %r15,VMX_MACHINE_T_GUEST_R15_OFFSET(%rdi)
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mov %rbx,CPU_CONTEXT_OFFSET_RBX(%rdi)
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mov %rcx,CPU_CONTEXT_OFFSET_RCX(%rdi)
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mov %rdx,CPU_CONTEXT_OFFSET_RDX(%rdi)
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mov %rbp,CPU_CONTEXT_OFFSET_RBP(%rdi)
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mov %rsi,CPU_CONTEXT_OFFSET_RSI(%rdi)
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mov %r8,CPU_CONTEXT_OFFSET_R8(%rdi)
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mov %r9,CPU_CONTEXT_OFFSET_R9(%rdi)
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mov %r10,CPU_CONTEXT_OFFSET_R10(%rdi)
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mov %r11,CPU_CONTEXT_OFFSET_R11(%rdi)
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mov %r12,CPU_CONTEXT_OFFSET_R12(%rdi)
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mov %r13,CPU_CONTEXT_OFFSET_R13(%rdi)
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mov %r14,CPU_CONTEXT_OFFSET_R14(%rdi)
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mov %r15,CPU_CONTEXT_OFFSET_R15(%rdi)
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/* Load guest RDI off host stack and into RDX */
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mov 0(%rsp),%rdx
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/* Save guest RDI to guest state area */
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mov %rdx,VMX_MACHINE_T_GUEST_RDI_OFFSET(%rdi)
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mov %rdx,CPU_CONTEXT_OFFSET_RDI(%rdi)
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/* Save RDI to RSI for later SPEC_CTRL save*/
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mov %rdi,%rsi
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@ -192,7 +192,7 @@ vm_eval_error:
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*/
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movl $0x00000048,%ecx
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rdmsr
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mov %rax,VMX_MACHINE_T_GUEST_SPEC_CTRL_OFFSET(%rsi)
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mov %rax,CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rsi)
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/* 0x1 = SPEC_ENABLE_IBRS */
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movl $0x1,%eax
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movl $0,%edx
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@ -215,7 +215,7 @@ ibrs_opt:
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*/
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movl $0x00000048,%ecx
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rdmsr
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mov %rax,VMX_MACHINE_T_GUEST_SPEC_CTRL_OFFSET(%rsi)
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mov %rax,CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rsi)
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/* 0x2 = SPEC_ENABLE_STIBP */
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movl $0x2,%eax
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movl $0,%edx
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@ -16,45 +16,61 @@
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#define NUM_GPRS 15
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#define GUEST_STATE_AREA_SIZE 512
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/* Indexes of GPRs saved / restored for guest */
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#define VMX_MACHINE_T_GUEST_RAX_INDEX 0
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#define VMX_MACHINE_T_GUEST_RBX_INDEX 1
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#define VMX_MACHINE_T_GUEST_RCX_INDEX 2
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#define VMX_MACHINE_T_GUEST_RDX_INDEX 3
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#define VMX_MACHINE_T_GUEST_RBP_INDEX 4
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#define VMX_MACHINE_T_GUEST_RSI_INDEX 5
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#define VMX_MACHINE_T_GUEST_R8_INDEX 6
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#define VMX_MACHINE_T_GUEST_R9_INDEX 7
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#define VMX_MACHINE_T_GUEST_R10_INDEX 8
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#define VMX_MACHINE_T_GUEST_R11_INDEX 9
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#define VMX_MACHINE_T_GUEST_R12_INDEX 10
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#define VMX_MACHINE_T_GUEST_R13_INDEX 11
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#define VMX_MACHINE_T_GUEST_R14_INDEX 12
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#define VMX_MACHINE_T_GUEST_R15_INDEX 13
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#define VMX_MACHINE_T_GUEST_RDI_INDEX 14
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#define CPU_CONTEXT_INDEX_RAX 0
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#define CPU_CONTEXT_INDEX_RBX 1
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#define CPU_CONTEXT_INDEX_RCX 2
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#define CPU_CONTEXT_INDEX_RDX 3
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#define CPU_CONTEXT_INDEX_RBP 4
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#define CPU_CONTEXT_INDEX_RSI 5
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#define CPU_CONTEXT_INDEX_R8 6
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#define CPU_CONTEXT_INDEX_R9 7
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#define CPU_CONTEXT_INDEX_R10 8
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#define CPU_CONTEXT_INDEX_R11 9
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#define CPU_CONTEXT_INDEX_R12 10
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#define CPU_CONTEXT_INDEX_R13 11
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#define CPU_CONTEXT_INDEX_R14 12
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#define CPU_CONTEXT_INDEX_R15 13
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#define CPU_CONTEXT_INDEX_RDI 14
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/* Offsets of GPRs for guest within the VCPU data structure */
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#define VMX_MACHINE_T_GUEST_RAX_OFFSET (VMX_MACHINE_T_GUEST_RAX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RBX_OFFSET (VMX_MACHINE_T_GUEST_RBX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RCX_OFFSET (VMX_MACHINE_T_GUEST_RCX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RDX_OFFSET (VMX_MACHINE_T_GUEST_RDX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RBP_OFFSET (VMX_MACHINE_T_GUEST_RBP_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RSI_OFFSET (VMX_MACHINE_T_GUEST_RSI_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RDI_OFFSET (VMX_MACHINE_T_GUEST_RDI_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R8_OFFSET (VMX_MACHINE_T_GUEST_R8_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R9_OFFSET (VMX_MACHINE_T_GUEST_R9_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R10_OFFSET (VMX_MACHINE_T_GUEST_R10_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R11_OFFSET (VMX_MACHINE_T_GUEST_R11_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R12_OFFSET (VMX_MACHINE_T_GUEST_R12_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R13_OFFSET (VMX_MACHINE_T_GUEST_R13_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R14_OFFSET (VMX_MACHINE_T_GUEST_R14_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R15_OFFSET (VMX_MACHINE_T_GUEST_R15_INDEX*REG_SIZE)
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/* Hard-coded offset of cr2 in struct run_context!! */
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#define VMX_MACHINE_T_GUEST_CR2_OFFSET (128)
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/* Hard-coded offset of cr2 in struct run_context!! */
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#define VMX_MACHINE_T_GUEST_SPEC_CTRL_OFFSET (192)
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#define CPU_CONTEXT_OFFSET_RAX 0
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#define CPU_CONTEXT_OFFSET_RBX 8
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#define CPU_CONTEXT_OFFSET_RCX 16
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#define CPU_CONTEXT_OFFSET_RDX 24
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#define CPU_CONTEXT_OFFSET_RBP 32
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#define CPU_CONTEXT_OFFSET_RSI 40
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#define CPU_CONTEXT_OFFSET_R8 48
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#define CPU_CONTEXT_OFFSET_R9 56
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#define CPU_CONTEXT_OFFSET_R10 64
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#define CPU_CONTEXT_OFFSET_R11 72
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#define CPU_CONTEXT_OFFSET_R12 80
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#define CPU_CONTEXT_OFFSET_R13 88
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#define CPU_CONTEXT_OFFSET_R14 96
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#define CPU_CONTEXT_OFFSET_R15 104
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#define CPU_CONTEXT_OFFSET_RDI 112
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#define CPU_CONTEXT_OFFSET_CR0 120
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#define CPU_CONTEXT_OFFSET_CR2 128
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#define CPU_CONTEXT_OFFSET_CR3 136
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#define CPU_CONTEXT_OFFSET_CR4 144
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#define CPU_CONTEXT_OFFSET_RIP 152
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#define CPU_CONTEXT_OFFSET_RSP 160
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#define CPU_CONTEXT_OFFSET_RFLAGS 168
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#define CPU_CONTEXT_OFFSET_TSC_OFFSET 184
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#define CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL 192
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#define CPU_CONTEXT_OFFSET_IA32_STAR 200
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#define CPU_CONTEXT_OFFSET_IA32_LSTAR 208
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#define CPU_CONTEXT_OFFSET_IA32_FMASK 216
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#define CPU_CONTEXT_OFFSET_IA32_KERNEL_GS_BASE 224
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#define CPU_CONTEXT_OFFSET_CS 280
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#define CPU_CONTEXT_OFFSET_SS 312
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#define CPU_CONTEXT_OFFSET_DS 344
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#define CPU_CONTEXT_OFFSET_ES 376
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#define CPU_CONTEXT_OFFSET_FS 408
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#define CPU_CONTEXT_OFFSET_GS 440
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#define CPU_CONTEXT_OFFSET_TR 472
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#define CPU_CONTEXT_OFFSET_IDTR 504
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#define CPU_CONTEXT_OFFSET_LDTR 536
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#define CPU_CONTEXT_OFFSET_GDTR 568
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#define CPU_CONTEXT_OFFSET_FXSTORE_GUEST_AREA 608
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/*sizes of various registers within the VCPU data structure */
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#define VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE GUEST_STATE_AREA_SIZE
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Reference in New Issue