modularization: boot component
Boot component prepares the very basic platform boot env. It finally call into platform initilization entries: - bsp_boot_init & cpu_secondary_init for start up - or restore_s3_context for wakeup this patch is the final one, it did some code clean up and move some definition from vm0_boot.h to boot_context.h. after this patch, the boot component include files: arch/x86/boot/cpu_primary.S arch/x86/boot/trampoline.S arch/x86/boot/cpu_save_boot_ctx.S arch/x86/boot/idt.S boot/reloc.c boot/include/reloc.h include/arch/x86/boot/idt.h include/arch/x86/boot/boot_context.h Tracked-On: #1842 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
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b54f23316a
commit
aa9af27338
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@ -4,11 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpu.h>
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#include <mmu.h>
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#include <gdt.h>
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#include <idt.h>
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#include <msr.h>
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/* NOTE:
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*
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@ -4,7 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm0_boot.h>
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#include <boot_context.h>
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.section entry, "ax"
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.align 8
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@ -13,7 +13,7 @@
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.global cpu_primary_save_32
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cpu_primary_save_32:
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/* save context from 32bit mode */
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lea vm0_boot_context, %eax
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lea boot_context, %eax
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sgdt BOOT_CTX_GDT_OFFSET(%eax)
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sidt BOOT_CTX_IDT_OFFSET(%eax)
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str BOOT_CTX_TR_SEL_OFFSET(%eax)
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@ -50,7 +50,7 @@ cpu_primary_save_32:
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.global cpu_primary_save_64
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cpu_primary_save_64:
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/* save context from 64bit mode */
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lea vm0_boot_context(%rip), %r8
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lea boot_context(%rip), %r8
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sgdt BOOT_CTX_GDT_OFFSET(%r8)
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sidt BOOT_CTX_IDT_OFFSET(%r8)
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str BOOT_CTX_TR_SEL_OFFSET(%r8)
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@ -90,8 +90,8 @@ cpu_primary_save_64:
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.text
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.align 8
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.global vm0_boot_context
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vm0_boot_context:
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.global boot_context
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boot_context:
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.rept SIZE_OF_BOOT_CTX
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.byte 0x00
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.endr
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@ -4,7 +4,6 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <gdt.h>
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#include <idt.h>
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.altmacro
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@ -15,10 +15,6 @@
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*/
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#include <spinlock.h>
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#include <gdt.h>
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#include <cpu.h>
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#include <mmu.h>
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#include <msr.h>
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/* NOTE:
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*
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@ -38,8 +34,6 @@
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*/
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.extern cpu_secondary_init
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.extern ld_bss_end
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.extern HOST_GDTR
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.section .trampoline_reset,"ax"
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@ -4,7 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#include <vm0_boot.h>
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#include <boot_context.h>
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#define CAT__(A,B) A ## B
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#define CAT_(A,B) CAT__(A,B)
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@ -6,6 +6,7 @@
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#include <hypervisor.h>
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#include <multiboot.h>
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#include <boot_context.h>
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#include <vm0_boot.h>
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#ifdef CONFIG_EFI_STUB
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@ -36,7 +37,7 @@ int uefi_sw_loader(struct acrn_vm *vm)
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{
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int ret = 0;
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struct acrn_vcpu *vcpu = get_primary_vcpu(vm);
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struct acrn_vcpu_regs *vcpu_regs = &vm0_boot_context;
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struct acrn_vcpu_regs *vcpu_regs = &boot_context;
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ASSERT(vm != NULL, "Incorrect argument");
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@ -47,8 +48,8 @@ int uefi_sw_loader(struct acrn_vm *vm)
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/* For UEFI platform, the bsp init regs come from two places:
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* 1. saved in efi_boot: gpregs, rip
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* 2. saved when HV started: other registers
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* We copy the info saved in efi_boot to vm0_boot_context and
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* init bsp with vm0_boot_context.
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* We copy the info saved in efi_boot to boot_context and
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* init bsp with boot_context.
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*/
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memcpy_s(&(vcpu_regs->gprs), sizeof(struct acrn_gp_regs),
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&(efi_ctx->vcpu_regs.gprs), sizeof(struct acrn_gp_regs));
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@ -6,6 +6,7 @@
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#include <hypervisor.h>
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#include <zeropage.h>
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#include <boot_context.h>
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#ifdef CONFIG_PARTITION_MODE
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static uint32_t create_e820_table(struct e820_entry *param_e820)
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@ -44,14 +45,14 @@ static void prepare_bsp_gdt(struct acrn_vm *vm)
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uint64_t gdt_base_hpa;
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void *gdt_base_hva;
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gdt_base_hpa = gpa2hpa(vm, vm0_boot_context.gdt.base);
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if (vm0_boot_context.gdt.base == gdt_base_hpa) {
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gdt_base_hpa = gpa2hpa(vm, boot_context.gdt.base);
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if (boot_context.gdt.base == gdt_base_hpa) {
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return;
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} else {
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gdt_base_hva = hpa2hva(gdt_base_hpa);
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gdt_len = ((size_t)vm0_boot_context.gdt.limit + 1U)/sizeof(uint8_t);
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gdt_len = ((size_t)boot_context.gdt.limit + 1U)/sizeof(uint8_t);
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(void )memcpy_s(gdt_base_hva, gdt_len, hpa2hva(vm0_boot_context.gdt.base), gdt_len);
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(void )memcpy_s(gdt_base_hva, gdt_len, hpa2hva(boot_context.gdt.base), gdt_len);
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}
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return;
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@ -116,7 +117,7 @@ int general_sw_loader(struct acrn_vm *vm)
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pr_dbg("Loading guest to run-time location");
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prepare_bsp_gdt(vm);
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set_vcpu_regs(vcpu, &vm0_boot_context);
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set_vcpu_regs(vcpu, &boot_context);
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/* calculate the kernel entry point */
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zeropage = (struct zero_page *)sw_kernel->kernel_src_addr;
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@ -0,0 +1,51 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_CTX_H
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#define BOOT_CTX_H
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#ifdef ASSEMBLER
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#define BOOT_CTX_CR0_OFFSET 176
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#define BOOT_CTX_CR3_OFFSET 192
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#define BOOT_CTX_CR4_OFFSET 184
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#define BOOT_CTX_IDT_OFFSET 144
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#define BOOT_CTX_GDT_OFFSET 128
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#define BOOT_CTX_LDT_SEL_OFFSET 280
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#define BOOT_CTX_TR_SEL_OFFSET 282
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#define BOOT_CTX_CS_SEL_OFFSET 268
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#define BOOT_CTX_SS_SEL_OFFSET 270
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#define BOOT_CTX_DS_SEL_OFFSET 272
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#define BOOT_CTX_ES_SEL_OFFSET 274
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#define BOOT_CTX_FS_SEL_OFFSET 276
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#define BOOT_CTX_GS_SEL_OFFSET 278
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#define BOOT_CTX_CS_AR_OFFSET 248
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#define BOOT_CTX_CS_LIMIT_OFFSET 252
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#define BOOT_CTX_EFER_LOW_OFFSET 200
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#define BOOT_CTX_EFER_HIGH_OFFSET 204
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#define SIZE_OF_BOOT_CTX 296
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#else
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#define BOOT_CTX_CR0_OFFSET 176U
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#define BOOT_CTX_CR3_OFFSET 192U
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#define BOOT_CTX_CR4_OFFSET 184U
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#define BOOT_CTX_IDT_OFFSET 144U
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#define BOOT_CTX_GDT_OFFSET 128U
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#define BOOT_CTX_LDT_SEL_OFFSET 280U
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#define BOOT_CTX_TR_SEL_OFFSET 282U
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#define BOOT_CTX_CS_SEL_OFFSET 268U
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#define BOOT_CTX_SS_SEL_OFFSET 270U
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#define BOOT_CTX_DS_SEL_OFFSET 272U
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#define BOOT_CTX_ES_SEL_OFFSET 274U
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#define BOOT_CTX_FS_SEL_OFFSET 276U
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#define BOOT_CTX_GS_SEL_OFFSET 278U
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#define BOOT_CTX_CS_AR_OFFSET 248U
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#define BOOT_CTX_CS_LIMIT_OFFSET 252U
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#define BOOT_CTX_EFER_LOW_OFFSET 200U
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#define BOOT_CTX_EFER_HIGH_OFFSET 204U
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#define SIZE_OF_BOOT_CTX 296U
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struct acrn_vcpu_regs;
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extern struct acrn_vcpu_regs boot_context;
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#endif /* ASSEMBLER */
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#endif /* BOOT_CTX_H */
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@ -220,7 +220,6 @@ int copy_from_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
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*/
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int copy_to_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
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uint32_t size, uint32_t *err_code, uint64_t *fault_addr);
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extern struct acrn_vcpu_regs vm0_boot_context;
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/**
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* @}
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*/
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#ifndef VM0_BOOT_H
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#define VM0_BOOT_H
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#ifdef ASSEMBLER
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#define BOOT_CTX_CR0_OFFSET 176
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#define BOOT_CTX_CR3_OFFSET 192
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#define BOOT_CTX_CR4_OFFSET 184
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#define BOOT_CTX_IDT_OFFSET 144
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#define BOOT_CTX_GDT_OFFSET 128
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#define BOOT_CTX_LDT_SEL_OFFSET 280
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#define BOOT_CTX_TR_SEL_OFFSET 282
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#define BOOT_CTX_CS_SEL_OFFSET 268
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#define BOOT_CTX_SS_SEL_OFFSET 270
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#define BOOT_CTX_DS_SEL_OFFSET 272
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#define BOOT_CTX_ES_SEL_OFFSET 274
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#define BOOT_CTX_FS_SEL_OFFSET 276
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#define BOOT_CTX_GS_SEL_OFFSET 278
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#define BOOT_CTX_CS_AR_OFFSET 248
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#define BOOT_CTX_CS_LIMIT_OFFSET 252
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#define BOOT_CTX_EFER_LOW_OFFSET 200
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#define BOOT_CTX_EFER_HIGH_OFFSET 204
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#define SIZE_OF_BOOT_CTX 296
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#else
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#define BOOT_CTX_CR0_OFFSET 176U
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#define BOOT_CTX_CR3_OFFSET 192U
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#define BOOT_CTX_CR4_OFFSET 184U
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#define BOOT_CTX_IDT_OFFSET 144U
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#define BOOT_CTX_GDT_OFFSET 128U
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#define BOOT_CTX_LDT_SEL_OFFSET 280U
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#define BOOT_CTX_TR_SEL_OFFSET 282U
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#define BOOT_CTX_CS_SEL_OFFSET 268U
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#define BOOT_CTX_SS_SEL_OFFSET 270U
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#define BOOT_CTX_DS_SEL_OFFSET 272U
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#define BOOT_CTX_ES_SEL_OFFSET 274U
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#define BOOT_CTX_FS_SEL_OFFSET 276U
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#define BOOT_CTX_GS_SEL_OFFSET 278U
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#define BOOT_CTX_CS_AR_OFFSET 248U
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#define BOOT_CTX_CS_LIMIT_OFFSET 252U
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#define BOOT_CTX_EFER_LOW_OFFSET 200U
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#define BOOT_CTX_EFER_HIGH_OFFSET 204U
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#define SIZE_OF_BOOT_CTX 296U
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#ifdef CONFIG_EFI_STUB
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struct efi_context {
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struct acrn_vcpu_regs vcpu_regs;
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void *get_rsdp_from_uefi(void);
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void *get_ap_trampoline_buf(void);
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#endif
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#endif /* ASSEMBLER */
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#endif /* VM0_BOOT_H */
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