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acrn-hypervisor
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modularization: boot component 

Boot component prepares the very basic platform boot env. It finally call
into platform initilization entries:

- bsp_boot_init & cpu_secondary_init for start up
- or restore_s3_context for wakeup

this patch is the final one, it did some code clean up and move some definition
from vm0_boot.h to boot_context.h.

after this patch, the boot component include files:
arch/x86/boot/cpu_primary.S
arch/x86/boot/trampoline.S
arch/x86/boot/cpu_save_boot_ctx.S
arch/x86/boot/idt.S
boot/reloc.c
boot/include/reloc.h
include/arch/x86/boot/idt.h
include/arch/x86/boot/boot_context.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Jason Chen CJ 2018-11-30 20:20:06 +08:00 committed by wenlingz
parent b54f23316a
commit aa9af27338
10 changed files with 68 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hypervisor/arch/x86/boot/cpu_primary.S
View File

@ -4,11 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <cpu.h>
#include <mmu.h>
#include <gdt.h>
#include <idt.h>
#include <msr.h>
/* NOTE:
*

10
hypervisor/arch/x86/boot/cpu_save_boot_ctx.S
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm0_boot.h>
#include <boot_context.h>
.section entry, "ax"
.align 8
@ -13,7 +13,7 @@
.global cpu_primary_save_32
cpu_primary_save_32:
/* save context from 32bit mode */
lea vm0_boot_context, %eax
lea boot_context, %eax
sgdt BOOT_CTX_GDT_OFFSET(%eax)
sidt BOOT_CTX_IDT_OFFSET(%eax)
str BOOT_CTX_TR_SEL_OFFSET(%eax)
@ -50,7 +50,7 @@ cpu_primary_save_32:
.global cpu_primary_save_64
cpu_primary_save_64:
/* save context from 64bit mode */
lea vm0_boot_context(%rip), %r8
lea boot_context(%rip), %r8
sgdt BOOT_CTX_GDT_OFFSET(%r8)
sidt BOOT_CTX_IDT_OFFSET(%r8)
str BOOT_CTX_TR_SEL_OFFSET(%r8)
@ -90,8 +90,8 @@ cpu_primary_save_64:
.text
.align 8
.global vm0_boot_context
vm0_boot_context:
.global boot_context
boot_context:
.rept SIZE_OF_BOOT_CTX
.byte 0x00
.endr

1
hypervisor/arch/x86/boot/idt.S
View File

@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <gdt.h>
#include <idt.h>
.altmacro

6
hypervisor/arch/x86/boot/trampoline.S
View File

@ -15,10 +15,6 @@
*/
#include <spinlock.h>
#include <gdt.h>
#include <cpu.h>
#include <mmu.h>
#include <msr.h>
/* NOTE:
*
@ -38,8 +34,6 @@
*/
.extern cpu_secondary_init
.extern ld_bss_end
.extern HOST_GDTR
.section .trampoline_reset,"ax"

2
hypervisor/arch/x86/static_checks.c
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <hypervisor.h>
#include <vm0_boot.h>
#include <boot_context.h>
#define CAT__(A,B) A ## B
#define CAT_(A,B) CAT__(A,B)

7
hypervisor/bsp/uefi/uefi.c
View File

@ -6,6 +6,7 @@
#include <hypervisor.h>
#include <multiboot.h>
#include <boot_context.h>
#include <vm0_boot.h>
#ifdef CONFIG_EFI_STUB
@ -36,7 +37,7 @@ int uefi_sw_loader(struct acrn_vm *vm)
{
int ret = 0;
struct acrn_vcpu *vcpu = get_primary_vcpu(vm);
struct acrn_vcpu_regs *vcpu_regs = &vm0_boot_context;
struct acrn_vcpu_regs *vcpu_regs = &boot_context;
ASSERT(vm != NULL, "Incorrect argument");
@ -47,8 +48,8 @@ int uefi_sw_loader(struct acrn_vm *vm)
/* For UEFI platform, the bsp init regs come from two places:
* 1. saved in efi_boot: gpregs, rip
* 2. saved when HV started: other registers
* We copy the info saved in efi_boot to vm0_boot_context and
* init bsp with vm0_boot_context.
* We copy the info saved in efi_boot to boot_context and
* init bsp with boot_context.
*/
memcpy_s(&(vcpu_regs->gprs), sizeof(struct acrn_gp_regs),
&(efi_ctx->vcpu_regs.gprs), sizeof(struct acrn_gp_regs));

11
hypervisor/common/vm_load.c
View File

@ -6,6 +6,7 @@
#include <hypervisor.h>
#include <zeropage.h>
#include <boot_context.h>
#ifdef CONFIG_PARTITION_MODE
static uint32_t create_e820_table(struct e820_entry *param_e820)
@ -44,14 +45,14 @@ static void prepare_bsp_gdt(struct acrn_vm *vm)
uint64_t gdt_base_hpa;
void *gdt_base_hva;
gdt_base_hpa = gpa2hpa(vm, vm0_boot_context.gdt.base);
if (vm0_boot_context.gdt.base == gdt_base_hpa) {
gdt_base_hpa = gpa2hpa(vm, boot_context.gdt.base);
if (boot_context.gdt.base == gdt_base_hpa) {
return;
} else {
gdt_base_hva = hpa2hva(gdt_base_hpa);
gdt_len = ((size_t)vm0_boot_context.gdt.limit + 1U)/sizeof(uint8_t);
gdt_len = ((size_t)boot_context.gdt.limit + 1U)/sizeof(uint8_t);
(void )memcpy_s(gdt_base_hva, gdt_len, hpa2hva(vm0_boot_context.gdt.base), gdt_len);
(void )memcpy_s(gdt_base_hva, gdt_len, hpa2hva(boot_context.gdt.base), gdt_len);
}
return;
@ -116,7 +117,7 @@ int general_sw_loader(struct acrn_vm *vm)
pr_dbg("Loading guest to run-time location");
prepare_bsp_gdt(vm);
set_vcpu_regs(vcpu, &vm0_boot_context);
set_vcpu_regs(vcpu, &boot_context);
/* calculate the kernel entry point */
zeropage = (struct zero_page *)sw_kernel->kernel_src_addr;

51
hypervisor/include/arch/x86/boot/boot_context.h Normal file
View File

@ -0,0 +1,51 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BOOT_CTX_H
#define BOOT_CTX_H
#ifdef ASSEMBLER
#define BOOT_CTX_CR0_OFFSET 176
#define BOOT_CTX_CR3_OFFSET 192
#define BOOT_CTX_CR4_OFFSET 184
#define BOOT_CTX_IDT_OFFSET 144
#define BOOT_CTX_GDT_OFFSET 128
#define BOOT_CTX_LDT_SEL_OFFSET 280
#define BOOT_CTX_TR_SEL_OFFSET 282
#define BOOT_CTX_CS_SEL_OFFSET 268
#define BOOT_CTX_SS_SEL_OFFSET 270
#define BOOT_CTX_DS_SEL_OFFSET 272
#define BOOT_CTX_ES_SEL_OFFSET 274
#define BOOT_CTX_FS_SEL_OFFSET 276
#define BOOT_CTX_GS_SEL_OFFSET 278
#define BOOT_CTX_CS_AR_OFFSET 248
#define BOOT_CTX_CS_LIMIT_OFFSET 252
#define BOOT_CTX_EFER_LOW_OFFSET 200
#define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
#else
#define BOOT_CTX_CR0_OFFSET 176U
#define BOOT_CTX_CR3_OFFSET 192U
#define BOOT_CTX_CR4_OFFSET 184U
#define BOOT_CTX_IDT_OFFSET 144U
#define BOOT_CTX_GDT_OFFSET 128U
#define BOOT_CTX_LDT_SEL_OFFSET 280U
#define BOOT_CTX_TR_SEL_OFFSET 282U
#define BOOT_CTX_CS_SEL_OFFSET 268U
#define BOOT_CTX_SS_SEL_OFFSET 270U
#define BOOT_CTX_DS_SEL_OFFSET 272U
#define BOOT_CTX_ES_SEL_OFFSET 274U
#define BOOT_CTX_FS_SEL_OFFSET 276U
#define BOOT_CTX_GS_SEL_OFFSET 278U
#define BOOT_CTX_CS_AR_OFFSET 248U
#define BOOT_CTX_CS_LIMIT_OFFSET 252U
#define BOOT_CTX_EFER_LOW_OFFSET 200U
#define BOOT_CTX_EFER_HIGH_OFFSET 204U
#define SIZE_OF_BOOT_CTX 296U
struct acrn_vcpu_regs;
extern struct acrn_vcpu_regs boot_context;
#endif /* ASSEMBLER */
#endif /* BOOT_CTX_H */

1
hypervisor/include/arch/x86/guest/guest.h
View File

@ -220,7 +220,6 @@ int copy_from_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
*/
int copy_to_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
uint32_t size, uint32_t *err_code, uint64_t *fault_addr);
extern struct acrn_vcpu_regs vm0_boot_context;
/**
* @}
*/

41
hypervisor/include/arch/x86/guest/vm0_boot.h
View File

@ -7,45 +7,6 @@
#ifndef VM0_BOOT_H
#define VM0_BOOT_H
#ifdef ASSEMBLER
#define BOOT_CTX_CR0_OFFSET 176
#define BOOT_CTX_CR3_OFFSET 192
#define BOOT_CTX_CR4_OFFSET 184
#define BOOT_CTX_IDT_OFFSET 144
#define BOOT_CTX_GDT_OFFSET 128
#define BOOT_CTX_LDT_SEL_OFFSET 280
#define BOOT_CTX_TR_SEL_OFFSET 282
#define BOOT_CTX_CS_SEL_OFFSET 268
#define BOOT_CTX_SS_SEL_OFFSET 270
#define BOOT_CTX_DS_SEL_OFFSET 272
#define BOOT_CTX_ES_SEL_OFFSET 274
#define BOOT_CTX_FS_SEL_OFFSET 276
#define BOOT_CTX_GS_SEL_OFFSET 278
#define BOOT_CTX_CS_AR_OFFSET 248
#define BOOT_CTX_CS_LIMIT_OFFSET 252
#define BOOT_CTX_EFER_LOW_OFFSET 200
#define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
#else
#define BOOT_CTX_CR0_OFFSET 176U
#define BOOT_CTX_CR3_OFFSET 192U
#define BOOT_CTX_CR4_OFFSET 184U
#define BOOT_CTX_IDT_OFFSET 144U
#define BOOT_CTX_GDT_OFFSET 128U
#define BOOT_CTX_LDT_SEL_OFFSET 280U
#define BOOT_CTX_TR_SEL_OFFSET 282U
#define BOOT_CTX_CS_SEL_OFFSET 268U
#define BOOT_CTX_SS_SEL_OFFSET 270U
#define BOOT_CTX_DS_SEL_OFFSET 272U
#define BOOT_CTX_ES_SEL_OFFSET 274U
#define BOOT_CTX_FS_SEL_OFFSET 276U
#define BOOT_CTX_GS_SEL_OFFSET 278U
#define BOOT_CTX_CS_AR_OFFSET 248U
#define BOOT_CTX_CS_LIMIT_OFFSET 252U
#define BOOT_CTX_EFER_LOW_OFFSET 200U
#define BOOT_CTX_EFER_HIGH_OFFSET 204U
#define SIZE_OF_BOOT_CTX 296U
#ifdef CONFIG_EFI_STUB
struct efi_context {
struct acrn_vcpu_regs vcpu_regs;
@ -56,5 +17,5 @@ struct efi_context {
void *get_rsdp_from_uefi(void);
void *get_ap_trampoline_buf(void);
#endif
#endif /* ASSEMBLER */
#endif /* VM0_BOOT_H */