HV: support up to 7 post launched VMs for industry scenario
In industry scenario, hypervisor will support 1 post-launched RT VM and 1 post-launched kata VM and up to 5 post-launched standard VMs; Tracked-On: #4661 Signed-off-by: Victor Sun <victor.sun@intel.com>
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Victor Sun
wenlingz
parent
09212cf4b6
commit
a90890e9c7
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@ -8,8 +8,9 @@ config SCENARIO
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sdc will have one pre-launched SOS VM and one post-launched VM;
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sdc2: Extended scenario for automotive Software Defined Cockpit system.
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sdc2 will have one pre-launched SOS VM and up to three post-launched VMs;
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industry: Typical scenario for industry usage with 3 VMs: one pre-launched SOS VM,
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one post-launched Standard VM for HMI, one post-launched RT VM for real-time control.
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industry: Typical scenario for industry usage with 8 VMs: one pre-launched SOS VM,
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one post-launched KATA VM, one post-launched RT VM for real-time control,
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and up to five post-launched Standard VMs;
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hybrid: Typical scenario for hybrid usage with 3 VMs: one pre-launched VM,
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one pre-launched SOS VM and one post-launched Standard VM;
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logical_partition: Typical scenario that run two isolated pre-launched VMs;
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@ -194,8 +195,8 @@ config HV_RAM_START
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config HV_RAM_SIZE
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hex "Size of the RAM region used by the hypervisor"
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range 0x1000000 0x10000000
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default 0x0b800000
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range 0x1000000 0x20000000
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default 0x14000000
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help
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A 64-bit integer indicating the size of RAM used by the hypervisor.
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It is ensured at link time that the footprint of the hypervisor
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@ -35,6 +35,14 @@
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#define POST_STANDARD_VM_UUID3 {0x38U, 0x15U, 0x88U, 0x21U, 0x52U, 0x08U, 0x40U, 0x05U, \
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0xb7U, 0x2aU, 0x8aU, 0x60U, 0x9eU, 0x41U, 0x90U, 0xd0U}
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/* a6750180-f87a-48d2-91d9-4e7f62b6519e */
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#define POST_STANDARD_VM_UUID4 {0xa6U, 0x75U, 0x01U, 0x80U, 0xf8U, 0x7aU, 0x48U, 0xd2U, \
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0x91U, 0xd9U, 0x4eU, 0x7fU, 0x62U, 0xb6U, 0x51U, 0x9eU}
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/* d1816e4a-a9bb-4cb4-a066-3f1a8a5ce73f */
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#define POST_STANDARD_VM_UUID5 {0xd1U, 0x81U, 0x6eU, 0x4aU, 0xa9U, 0xbbU, 0x4cU, 0xb4U, \
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0xa0U, 0x66U, 0x3fU, 0x1aU, 0x8aU, 0x5cU, 0xe7U, 0x3fU}
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/* 495ae2e5-2603-4d64-af76-d4bc5a8ec0e5 */
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#define POST_RTVM_UUID1 {0x49U, 0x5aU, 0xe2U, 0xe5U, 0x26U, 0x03U, 0x4dU, 0x64U, \
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0xafU, 0x76U, 0xd4U, 0xbcU, 0x5aU, 0x8eU, 0xc0U, 0xe5U}
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@ -50,11 +50,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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{ /* VM2 */
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CONFIG_POST_RT_VM(1),
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/* The hard RTVM must be launched as VM2 */
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.guest_flags = 0UL,
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.vcpu_num = 2U,
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.vcpu_affinity = VM2_CONFIG_VCPU_AFFINITY,
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@ -71,4 +69,74 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
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.t_vuart.vuart_id = 1U,
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},
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},
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{ /* VM3 */
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CONFIG_POST_STD_VM(2),
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.vcpu_num = 1U,
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.vcpu_affinity = VM3_CONFIG_VCPU_AFFINITY,
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = COM1_BASE,
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.irq = COM1_IRQ,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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{ /* VM4 */
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CONFIG_POST_STD_VM(3),
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.vcpu_num = 1U,
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.vcpu_affinity = VM4_CONFIG_VCPU_AFFINITY,
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = COM1_BASE,
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.irq = COM1_IRQ,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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{ /* VM5 */
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CONFIG_POST_STD_VM(4),
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.vcpu_num = 1U,
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.vcpu_affinity = VM5_CONFIG_VCPU_AFFINITY,
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = COM1_BASE,
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.irq = COM1_IRQ,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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{ /* VM6 */
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CONFIG_POST_STD_VM(5),
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.vcpu_num = 1U,
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.vcpu_affinity = VM6_CONFIG_VCPU_AFFINITY,
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = COM1_BASE,
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.irq = COM1_IRQ,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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{ /* VM7 */
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CONFIG_KATA_VM(1),
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.vcpu_num = 1U,
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.vcpu_affinity = VM7_CONFIG_VCPU_AFFINITY,
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = COM1_BASE,
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.irq = COM1_IRQ,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = INVALID_COM_BASE,
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}
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},
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};
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@ -15,8 +15,8 @@
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*/
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#define PRE_VM_NUM 0U
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#define SOS_VM_NUM 1U
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#define MAX_POST_VM_NUM 2U
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#define CONFIG_MAX_KATA_VM_NUM 0U
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#define MAX_POST_VM_NUM 7U
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#define CONFIG_MAX_KATA_VM_NUM 1U
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/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
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#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
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@ -37,5 +37,10 @@
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#define VM1_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(0U), AFFINITY_CPU(1U)}
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#define VM2_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(2U), AFFINITY_CPU(3U)}
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#define VM3_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(1U)}
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#define VM4_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(1U)}
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#define VM5_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(1U)}
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#define VM6_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(1U)}
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#define VM7_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(1U)}
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#endif /* VM_CONFIGURATIONS_H */
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