From a4eebb0ef80cea7274798c369e7eb1bdd5a75844 Mon Sep 17 00:00:00 2001 From: Yin Fengwei Date: Sat, 21 Jul 2018 22:53:10 +0800 Subject: [PATCH] hv: cleanup inline assembly code in vmx.c a little bit 1. We could explicitly use specific register to avoid one more register allocated. 2. If we explicitly assign register, it's not neccessary to add the register in clobber list according to gcc mannual. 3. For vmptrld, we add memory to clobber list also. Signed-off-by: Yin Fengwei Reviewed-by: Edwin Zhai Acked-by: Eddie Dong --- hypervisor/arch/x86/vmx.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/hypervisor/arch/x86/vmx.c b/hypervisor/arch/x86/vmx.c index b11ae63b5..c8c9a05e2 100644 --- a/hypervisor/arch/x86/vmx.c +++ b/hypervisor/arch/x86/vmx.c @@ -55,12 +55,12 @@ static inline int exec_vmxon(void *addr) /* Ensure previous operations successful */ if (status == 0) { /* Turn VMX on */ - asm volatile ("mov %1, %%rax\n" + asm volatile ( "vmxon (%%rax)\n" "pushfq\n" "pop %0\n":"=r" (rflags) - : "r"(addr) - : "%rax", "cc", "memory"); + : "a"(addr) + : "cc", "memory"); /* if carry and zero flags are clear operation success */ if ((rflags & (RFLAGS_C | RFLAGS_Z)) != 0U) { @@ -153,12 +153,12 @@ int exec_vmclear(void *addr) ASSERT(status == 0, "Incorrect arguments"); asm volatile ( - "mov %1, %%rax\n" "vmclear (%%rax)\n" "pushfq\n" - "pop %0\n":"=r" (rflags) - : "r"(addr) - : "%rax", "cc", "memory"); + "pop %0\n" + :"=r" (rflags) + : "a"(addr) + : "cc", "memory"); /* if carry and zero flags are clear operation success */ if ((rflags & (RFLAGS_C | RFLAGS_Z)) != 0U) { @@ -179,13 +179,12 @@ int exec_vmptrld(void *addr) ASSERT(status == 0, "Incorrect arguments"); asm volatile ( - "mov %1, %%rax\n" "vmptrld (%%rax)\n" "pushfq\n" "pop %0\n" : "=r" (rflags) - : "r"(addr) - : "%rax", "cc"); + : "a"(addr) + : "cc", "memory"); /* if carry and zero flags are clear operation success */ if ((rflags & (RFLAGS_C | RFLAGS_Z)) != 0U) { @@ -1153,7 +1152,7 @@ static void init_host_state(__unused struct vcpu *vcpu) (((trbase_lo >> 56U) & 0xffUL) << 24U); /* SS segment override for upper32 bits of base in ia32e mode */ - asm volatile ("mov %0,%%rax\n" + asm volatile ( ".byte 0x36\n" "movq 8(%%rax),%%rax\n":"=a" (trbase_hi):"0"(trbase)); realtrbase = realtrbase | (trbase_hi << 32U);