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dm: e820: reserve memory range for EPC resource 

Reserved 128MB memory range for EPC resource in E820 table, starting
from 0x80000000.
Need to align the base address b/t DM and HV.
For hypervisor, the base address will be specified in epc field in
vm_configurations.c

Tracked-On: #3179
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu 2019-05-22 15:36:28 +08:00 committed by ACRN System Integration
parent 7a915dc397
commit a3073175a6
2 changed files with 13 additions and 5 deletions
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14
devicemodel/core/sw_load_common.c
View File

@ -55,9 +55,10 @@ static char bootargs[BOOT_ARG_LEN];
* 1: 0xA0000 - 0x100000 (reserved) 0x60000
* 2: 0x100000 - lowmem RAM lowmem - 1MB
* 3: lowmem - 0x80000000 (reserved) 2GB - lowmem
* 4: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
* 5: 0x100000000 - 0x140000000 64-bit PCI hole 1GB
* 6: 0x140000000 - highmem RAM highmem - 5GB
* 4: 0x80000000 - 0x88000000 (reserved) 128MB
* 5: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
* 6: 0x100000000 - 0x140000000 64-bit PCI hole 1GB
* 7: 0x140000000 - highmem RAM highmem - 5GB
*/
const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
{ /* 0 to video memory */
@ -84,6 +85,13 @@ const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
.type = E820_TYPE_RESERVED
},
{
/* reserve for PRM resource */
.baseaddr = 0x80000000,
.length = 0x8000000,
.type = E820_TYPE_RESERVED
},
{ /* ECFG_BASE to 4GB */
.baseaddr = PCI_EMUL_ECFG_BASE,
.length = (4 * GB) - PCI_EMUL_ECFG_BASE,

4
devicemodel/include/sw_load.h
View File

@ -39,9 +39,9 @@
#define E820_TYPE_ACPI_NVS 4 /* EFI 10 */
#define E820_TYPE_UNUSABLE 5 /* EFI 8 */
#define NUM_E820_ENTRIES 7
#define NUM_E820_ENTRIES 8
#define LOWRAM_E820_ENTRY 2
#define HIGHRAM_E820_ENTRY 6
#define HIGHRAM_E820_ENTRY 7
/* Defines a single entry in an E820 memory map. */
struct e820_entry {