dm: Use new ptdev interrupt management ioctls
IC_SET_PTDEV_INTR_INFO -> ACRN_IOCTL_SET_PTDEV_INTR IC_RESET_PTDEV_INTR_INFO -> ACRN_IOCTL_RESET_PTDEV_INTR struct ic_ptdev_irq -> struct acrn_ptdev_irq IRQ_INTX -> ACRN_PTDEV_IRQ_INTX IRQ_MSI -> ACRN_PTDEV_IRQ_MSI Tracked-On: #6282 Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
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7e01d90b87
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9d67745037
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@ -611,33 +611,33 @@ int
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vm_set_ptdev_intx_info(struct vmctx *ctx, uint16_t virt_bdf, uint16_t phys_bdf,
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vm_set_ptdev_intx_info(struct vmctx *ctx, uint16_t virt_bdf, uint16_t phys_bdf,
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int virt_pin, int phys_pin, bool pic_pin)
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int virt_pin, int phys_pin, bool pic_pin)
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{
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{
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struct ic_ptdev_irq ptirq;
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struct acrn_ptdev_irq ptirq;
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bzero(&ptirq, sizeof(ptirq));
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bzero(&ptirq, sizeof(ptirq));
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ptirq.type = IRQ_INTX;
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ptirq.type = ACRN_PTDEV_IRQ_INTX;
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ptirq.virt_bdf = virt_bdf;
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ptirq.virt_bdf = virt_bdf;
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ptirq.phys_bdf = phys_bdf;
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ptirq.phys_bdf = phys_bdf;
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ptirq.intx.virt_pin = virt_pin;
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ptirq.intx.virt_pin = virt_pin;
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ptirq.intx.phys_pin = phys_pin;
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ptirq.intx.phys_pin = phys_pin;
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ptirq.intx.is_pic_pin = pic_pin;
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ptirq.intx.is_pic_pin = pic_pin;
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return ioctl(ctx->fd, IC_SET_PTDEV_INTR_INFO, &ptirq);
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return ioctl(ctx->fd, ACRN_IOCTL_SET_PTDEV_INTR, &ptirq);
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}
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}
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int
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int
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vm_reset_ptdev_intx_info(struct vmctx *ctx, uint16_t virt_bdf, uint16_t phys_bdf,
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vm_reset_ptdev_intx_info(struct vmctx *ctx, uint16_t virt_bdf, uint16_t phys_bdf,
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int virt_pin, bool pic_pin)
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int virt_pin, bool pic_pin)
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{
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{
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struct ic_ptdev_irq ptirq;
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struct acrn_ptdev_irq ptirq;
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bzero(&ptirq, sizeof(ptirq));
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bzero(&ptirq, sizeof(ptirq));
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ptirq.type = IRQ_INTX;
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ptirq.type = ACRN_PTDEV_IRQ_INTX;
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ptirq.intx.virt_pin = virt_pin;
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ptirq.intx.virt_pin = virt_pin;
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ptirq.intx.is_pic_pin = pic_pin;
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ptirq.intx.is_pic_pin = pic_pin;
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ptirq.virt_bdf = virt_bdf;
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ptirq.virt_bdf = virt_bdf;
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ptirq.phys_bdf = phys_bdf;
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ptirq.phys_bdf = phys_bdf;
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return ioctl(ctx->fd, IC_RESET_PTDEV_INTR_INFO, &ptirq);
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return ioctl(ctx->fd, ACRN_IOCTL_RESET_PTDEV_INTR, &ptirq);
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}
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}
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int
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int
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@ -286,14 +286,14 @@ cfginitbar(struct vmctx *ctx, struct passthru_dev *ptdev)
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* return value:
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* return value:
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* -1 : fail
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* -1 : fail
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* >=0: succeed
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* >=0: succeed
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* IRQ_INTX(0): phy dev has no MSI support
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* ACRN_PTDEV_IRQ_INTX(0): phy dev has no MSI support
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* IRQ_MSI(1): phy dev has MSI support
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* ACRN_PTDEV_IRQ_MSI(1): phy dev has MSI support
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*/
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*/
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static int
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static int
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cfginit(struct vmctx *ctx, struct passthru_dev *ptdev, int bus,
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cfginit(struct vmctx *ctx, struct passthru_dev *ptdev, int bus,
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int slot, int func)
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int slot, int func)
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{
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{
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int irq_type = IRQ_MSI;
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int irq_type = ACRN_PTDEV_IRQ_MSI;
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char reset_path[60];
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char reset_path[60];
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int fd;
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int fd;
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@ -312,7 +312,7 @@ cfginit(struct vmctx *ctx, struct passthru_dev *ptdev, int bus,
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if (ptdev->msi.capoff == 0 && ptdev->msix.capoff == 0) {
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if (ptdev->msi.capoff == 0 && ptdev->msix.capoff == 0) {
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pr_dbg("MSI not supported for PCI %x/%x/%x",
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pr_dbg("MSI not supported for PCI %x/%x/%x",
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bus, slot, func);
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bus, slot, func);
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irq_type = IRQ_INTX;
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irq_type = ACRN_PTDEV_IRQ_INTX;
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}
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}
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/* If SOS kernel provides 'reset' entry in sysfs, related dev has some
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/* If SOS kernel provides 'reset' entry in sysfs, related dev has some
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@ -671,7 +671,7 @@ passthru_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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error = pci_emul_alloc_pbar(dev, vmsix_on_msi_bar_id, 0, PCIBAR_MEM32, 4096);
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error = pci_emul_alloc_pbar(dev, vmsix_on_msi_bar_id, 0, PCIBAR_MEM32, 4096);
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if (error < 0)
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if (error < 0)
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goto done;
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goto done;
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error = IRQ_MSI;
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error = ACRN_PTDEV_IRQ_MSI;
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}
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}
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if (ptdev->phys_bdf == PCI_BDF_GPU)
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if (ptdev->phys_bdf == PCI_BDF_GPU)
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@ -687,7 +687,7 @@ passthru_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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* Forge Guest to use MSI/MSIX in this case to mitigate IRQ sharing
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* Forge Guest to use MSI/MSIX in this case to mitigate IRQ sharing
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* issue
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* issue
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*/
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*/
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if (error != IRQ_MSI || keep_gsi) {
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if (error != ACRN_PTDEV_IRQ_MSI || keep_gsi) {
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/* Allocates the virq if ptdev only support INTx */
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/* Allocates the virq if ptdev only support INTx */
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pci_lintr_request(dev);
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pci_lintr_request(dev);
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@ -113,10 +113,10 @@
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/* PCI assignment*/
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/* PCI assignment*/
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#define IC_ID_PCI_BASE 0x50UL
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#define IC_ID_PCI_BASE 0x50UL
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#define IC_ASSIGN_PTDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x00)
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#define ACRN_IOCTL_SET_PTDEV_INTR \
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#define IC_DEASSIGN_PTDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x01)
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_IOW(ACRN_IOCTL_TYPE, 0x53, struct acrn_ptdev_irq)
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#define IC_VM_PCI_MSIX_REMAP _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x02)
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#define ACRN_IOCTL_RESET_PTDEV_INTR \
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#define IC_SET_PTDEV_INTR_INFO _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x03)
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_IOW(ACRN_IOCTL_TYPE, 0x54, struct acrn_ptdev_irq)
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#define IC_RESET_PTDEV_INTR_INFO _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x04)
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#define IC_RESET_PTDEV_INTR_INFO _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x04)
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#define IC_ASSIGN_PCIDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x05)
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#define IC_ASSIGN_PCIDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x05)
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#define IC_DEASSIGN_PCIDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x06)
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#define IC_DEASSIGN_PCIDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x06)
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@ -273,13 +273,15 @@ struct acrn_emul_dev {
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} __attribute__((aligned(8)));
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} __attribute__((aligned(8)));
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/* Type of interrupt of a passthrough device */
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#define ACRN_PTDEV_IRQ_INTX 0
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#define ACRN_PTDEV_IRQ_MSI 1
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#define ACRN_PTDEV_IRQ_MSIX 2
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/**
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/**
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* @brief pass thru device irq data structure
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* @brief pass thru device irq data structure
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*/
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*/
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struct ic_ptdev_irq {
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struct acrn_ptdev_irq {
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#define IRQ_INTX 0
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#define IRQ_MSI 1
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#define IRQ_MSIX 2
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/** irq type */
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/** irq type */
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uint32_t type;
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uint32_t type;
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/** virtual bdf description of pass thru device */
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/** virtual bdf description of pass thru device */
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