OrgACRN
/
acrn-hypervisor
mirror of https://github.com/projectacrn/acrn-hypervisor.git
1
0
Fork 0
Code Issues Releases Wiki Activity

HV: Remove the check pcpu active status when sending INIT 

Intel SDM Vol3 23.8 says:
  The INIT signal is blocked whenever a logical processor is in VMX root operation.
  It is not blocked in VMX nonroot operation. Instead, INITs cause VM exits

So, there is no side-effect to send INIT signal regardless of pcpu active status.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Kaige Fu 2019-04-01 16:50:13 +00:00 committed by wenlingz
parent f412d52546
commit 9c5e16987a
2 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
hypervisor/arch/x86/lapic.c
View File

@ -271,7 +271,6 @@ void send_single_ipi(uint16_t pcpu_id, uint32_t vector)
/**
* @pre pcpu_id < CONFIG_MAX_PCPU_NUM
* @pre target pCPU must be in active state
*
* @return None
*/
@ -279,12 +278,13 @@ void send_single_init(uint16_t pcpu_id)
{
union apic_icr icr;
if (is_pcpu_active(pcpu_id)) {
/*
* Intel SDM Vol3 23.8:
* The INIT signal is blocked whenever a logical processor is in VMX root operation.
* It is not blocked in VMX nonroot operation. Instead, INITs cause VM exits
*/
icr.value_32.hi_32 = per_cpu(lapic_id, pcpu_id);
icr.value_32.lo_32 = (INTR_LAPIC_ICR_PHYSICAL << 11U) | (INTR_LAPIC_ICR_INIT << 8U);
msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
} else {
ASSERT(false, "pCPU%u not in active", pcpu_id);
}
}

2
hypervisor/include/arch/x86/lapic.h
View File

@ -128,6 +128,8 @@ void send_single_ipi(uint16_t pcpu_id, uint32_t vector);
* @brief Send an INIT signal to a single pCPU
*
* @param[in] pcpu_id The id of destination physical cpu
*
* @return None
*/
void send_single_init(uint16_t pcpu_id);