HV: Remove the check pcpu active status when sending INIT
Intel SDM Vol3 23.8 says: The INIT signal is blocked whenever a logical processor is in VMX root operation. It is not blocked in VMX nonroot operation. Instead, INITs cause VM exits So, there is no side-effect to send INIT signal regardless of pcpu active status. Tracked-On: #2865 Signed-off-by: Kaige Fu <kaige.fu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
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@ -271,7 +271,6 @@ void send_single_ipi(uint16_t pcpu_id, uint32_t vector)
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/**
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* @pre pcpu_id < CONFIG_MAX_PCPU_NUM
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* @pre target pCPU must be in active state
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*
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* @return None
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*/
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@ -279,12 +278,13 @@ void send_single_init(uint16_t pcpu_id)
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{
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union apic_icr icr;
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if (is_pcpu_active(pcpu_id)) {
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icr.value_32.hi_32 = per_cpu(lapic_id, pcpu_id);
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icr.value_32.lo_32 = (INTR_LAPIC_ICR_PHYSICAL << 11U) | (INTR_LAPIC_ICR_INIT << 8U);
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/*
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* Intel SDM Vol3 23.8:
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* The INIT signal is blocked whenever a logical processor is in VMX root operation.
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* It is not blocked in VMX nonroot operation. Instead, INITs cause VM exits
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*/
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icr.value_32.hi_32 = per_cpu(lapic_id, pcpu_id);
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icr.value_32.lo_32 = (INTR_LAPIC_ICR_PHYSICAL << 11U) | (INTR_LAPIC_ICR_INIT << 8U);
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msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
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} else {
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ASSERT(false, "pCPU%u not in active", pcpu_id);
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}
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msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
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}
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@ -128,6 +128,8 @@ void send_single_ipi(uint16_t pcpu_id, uint32_t vector);
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* @brief Send an INIT signal to a single pCPU
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*
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* @param[in] pcpu_id The id of destination physical cpu
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*
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* @return None
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*/
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void send_single_init(uint16_t pcpu_id);
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