HV: remove IRQSTATE_ASSERT/IRQSTATE_DEASSERT/IRQSTATE_PULSE

- replace vpic/vioapic_xassert_irq() APIs
      with vpic/vioapic_set_irq()

   - unify the description of IRQ/PIN state in vpic. & vioapic.c

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/arch/x86/assign.c

@@ -359,9 +359,11 @@ static void ptdev_intr_handle_irq(struct vm *vm,
 		}
 
 		if (trigger_lvl) {
-			vioapic_assert_irq(vm, virt_sid->intx_id.pin);
+			vioapic_set_irq(vm, virt_sid->intx_id.pin,
+					GSI_SET_HIGH);
 		} else {
-			vioapic_pulse_irq(vm, virt_sid->intx_id.pin);
+			vioapic_set_irq(vm, virt_sid->intx_id.pin,
+					GSI_RAISING_PULSE);
 		}
 
 		dev_dbg(ACRN_DBG_PTIRQ,
@@ -378,9 +380,10 @@ static void ptdev_intr_handle_irq(struct vm *vm,
 		/* VPIN_PIC src means we have vpic enabled */
 		vpic_get_irq_trigger(vm, virt_sid->intx_id.pin, &trigger);
 		if (trigger == LEVEL_TRIGGER) {
-			vpic_assert_irq(vm, virt_sid->intx_id.pin);
+			vpic_set_irq(vm, virt_sid->intx_id.pin, GSI_SET_HIGH);
 		} else {
-			vpic_pulse_irq(vm, virt_sid->intx_id.pin);
+			vpic_set_irq(vm, virt_sid->intx_id.pin,
+					GSI_RAISING_PULSE);
 		}
 		break;
 	}
@@ -457,10 +460,10 @@ void ptdev_intx_ack(struct vm *vm, uint8_t virt_pin,
 	 */
 	switch (vpin_src) {
 	case PTDEV_VPIN_IOAPIC:
-		vioapic_deassert_irq(vm, virt_pin);
+		vioapic_set_irq(vm, virt_pin, GSI_SET_LOW);
 		break;
 	case PTDEV_VPIN_PIC:
-		vpic_deassert_irq(vm, virt_pin);
+		vpic_set_irq(vm, virt_pin, GSI_SET_LOW);
 	default:
 		/*
 		 * In this switch statement, vpin_src shall either be

hypervisor/common/hypercall.c

@@ -67,53 +67,6 @@ int32_t hcall_get_api_version(struct vm *vm, uint64_t param)
 	return 0;
 }
 
-/**
- *@pre Pointer vm shall point to VM0
- */
-static void
-handle_vpic_irqline(struct vm *vm, uint32_t irq, uint32_t operation)
-{
-	switch (operation) {
-	case GSI_SET_HIGH:
-		vpic_assert_irq(vm, irq);
-		break;
-	case GSI_SET_LOW:
-		vpic_deassert_irq(vm, irq);
-		break;
-	case GSI_RAISING_PULSE:
-		vpic_pulse_irq(vm, irq);
-	default:
-		/*
-		 * Gracefully return if prior case clauses have not been met.
-		 */
-		break;
-	}
-}
-
-/**
- *@pre Pointer vm shall point to VM0
- */
-static void
-handle_vioapic_irqline(struct vm *vm, uint32_t irq, uint32_t operation)
-{
-	switch (operation) {
-	case GSI_SET_HIGH:
-		vioapic_assert_irq(vm, irq);
-		break;
-	case GSI_SET_LOW:
-		vioapic_deassert_irq(vm, irq);
-		break;
-	case GSI_RAISING_PULSE:
-		vioapic_pulse_irq(vm, irq);
-		break;
-	default:
-		/*
-		 * Gracefully return if prior case clauses have not been met.
-		 */
-		break;
-	}
-}
-
 /**
  *@pre Pointer vm shall point to VM0
  */
@@ -147,19 +100,18 @@ handle_virt_irqline(struct vm *vm, uint16_t target_vmid,
 	switch (intr_type) {
 	case ACRN_INTR_TYPE_ISA:
 		/* Call vpic for pic injection */
-		handle_vpic_irqline(target_vm, param->pic_irq, operation);
+		vpic_set_irq(target_vm, param->pic_irq, operation);
 
 		/* call vioapic for ioapic injection if ioapic_irq != ~0U*/
 		if (param->ioapic_irq != (~0U)) {
 			/* handle IOAPIC irqline */
-			handle_vioapic_irqline(target_vm,
+			vioapic_set_irq(target_vm,
-				param->ioapic_irq, operation);
+					param->ioapic_irq, operation);
 		}
 		break;
 	case ACRN_INTR_TYPE_IOAPIC:
 		/* handle IOAPIC irqline */
-		handle_vioapic_irqline(target_vm,
+		vioapic_set_irq(target_vm, param->ioapic_irq, operation);
-				param->ioapic_irq, operation);
 		break;
 	default:
 		dev_dbg(ACRN_DBG_HYCALL, "vINTR inject failed. type=%d",
@@ -361,11 +313,11 @@ int32_t hcall_set_irqline(struct vm *vm, uint16_t vmid,
 
 	if (ops->nr_gsi < vpic_pincount()) {
 		/* Call vpic for pic injection */
-		handle_vpic_irqline(target_vm, ops->nr_gsi, ops->op);
+		vpic_set_irq(target_vm, ops->nr_gsi, ops->op);
 	}
 
 	/* handle IOAPIC irqline */
-	handle_vioapic_irqline(target_vm, ops->nr_gsi, ops->op);
+	vioapic_set_irq(target_vm, ops->nr_gsi, ops->op);
 
 	return 0;
 }

hypervisor/debug/vuart.c

@@ -123,13 +123,13 @@ static void vuart_toggle_intr(struct acrn_vuart *vu)
 	intr_reason = vuart_intr_reason(vu);
 
 	if (intr_reason != IIR_NOPEND) {
-		vpic_assert_irq(vu->vm, COM1_IRQ);
+		vpic_set_irq(vu->vm, COM1_IRQ, GSI_SET_HIGH);
 
-		vioapic_assert_irq(vu->vm, COM1_IRQ);
+		vioapic_set_irq(vu->vm, COM1_IRQ, GSI_SET_HIGH);
 
-		vpic_deassert_irq(vu->vm, COM1_IRQ);
+		vpic_set_irq(vu->vm, COM1_IRQ, GSI_SET_LOW);
 
-		vioapic_deassert_irq(vu->vm, COM1_IRQ);
+		vioapic_set_irq(vu->vm, COM1_IRQ, GSI_SET_LOW);
 	}
 }
 

hypervisor/dm/vioapic.c

@@ -120,21 +120,16 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, bool newstate)
 	}
 }
 
-enum irqstate {
-	IRQSTATE_ASSERT,
-	IRQSTATE_DEASSERT,
-	IRQSTATE_PULSE
-};
-
 /**
  * @pre irq < vioapic_pincount(vm)
- * @pre irqstate value shall be one of the folllowing values:
+ * @pre operation value shall be one of the folllowing values:
- *	IRQSTATE_ASSERT
+ *	GSI_SET_HIGH
- *	IRQSTATE_DEASSERT
+ *	GSI_SET_LOW
- *	IRQSTATE_PULSE
+ *	GSI_RAISING_PULSE
+ *	GSI_FALLING_PULSE
  */
-static void
+void
-vioapic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate)
+vioapic_set_irq(struct vm *vm, uint32_t irq, uint32_t operation)
 {
 	struct acrn_vioapic *vioapic;
 	uint32_t pin = irq;
@@ -142,44 +137,30 @@ vioapic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate)
 	vioapic = vm_ioapic(vm);
 
 	spinlock_obtain(&(vioapic->mtx));
-	switch (irqstate) {
+	switch (operation) {
-	case IRQSTATE_ASSERT:
+	case GSI_SET_HIGH:
 		vioapic_set_pinstate(vioapic, pin, true);
 		break;
-	case IRQSTATE_DEASSERT:
+	case GSI_SET_LOW:
 		vioapic_set_pinstate(vioapic, pin, false);
 		break;
-	case IRQSTATE_PULSE:
+	case GSI_RAISING_PULSE:
 		vioapic_set_pinstate(vioapic, pin, true);
 		vioapic_set_pinstate(vioapic, pin, false);
 		break;
+	case GSI_FALLING_PULSE:
+		vioapic_set_pinstate(vioapic, pin, false);
+		vioapic_set_pinstate(vioapic, pin, true);
+		break;
 	default:
 		/*
 		 * The function caller could guarantee the pre condition.
-		 * All the possible 'irqstate' has been handled in prior cases.
 		 */
 		break;
 	}
 	spinlock_release(&(vioapic->mtx));
 }
 
-void
-vioapic_assert_irq(struct vm *vm, uint32_t irq)
-{
-	vioapic_set_irqstate(vm, irq, IRQSTATE_ASSERT);
-}
-
-void vioapic_deassert_irq(struct vm *vm, uint32_t irq)
-{
-	vioapic_set_irqstate(vm, irq, IRQSTATE_DEASSERT);
-}
-
-void
-vioapic_pulse_irq(struct vm *vm, uint32_t irq)
-{
-	vioapic_set_irqstate(vm, irq, IRQSTATE_PULSE);
-}
-
 /*
  * Reset the vlapic's trigger-mode register to reflect the ioapic pin
  * configuration.

hypervisor/dm/vpic.c

@@ -31,12 +31,6 @@
 
 #define ACRN_DBG_PIC	6U
 
-enum irqstate {
-	IRQSTATE_ASSERT,
-	IRQSTATE_DEASSERT,
-	IRQSTATE_PULSE
-};
-
 #define NR_VPIC_PINS_PER_CHIP	8U
 #define NR_VPIC_PINS_TOTAL	16U
 #define VPIC_INVALID_PIN	0xffU
@@ -206,7 +200,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
 			 * to vioapic pin0 (irq2)
 			 * From MPSpec session 5.1
 			 */
-			vioapic_pulse_irq(vpic->vm, 0U);
+			vioapic_set_irq(vpic->vm, 0U, GSI_RAISING_PULSE);
 		}
 	} else {
 		dev_dbg(ACRN_DBG_PIC,
@@ -453,13 +447,13 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin, bool newstate
 
 /**
  * @pre irq < NR_VPIC_PINS_TOTAL
- * @pre irqstate value shall be one of the folllowing values:
+ * @pre operation value shall be one of the folllowing values:
- *	IRQSTATE_ASSERT
+ *	GSI_SET_HIGH
- *	IRQSTATE_DEASSERT
+ *	GSI_SET_LOW
- *	IRQSTATE_PULSE
+ *	GSI_RAISING_PULSE
+ *	GSI_FALLING_PULSE
  */
-static void vpic_set_irqstate(struct vm *vm, uint32_t irq,
+void vpic_set_irq(struct vm *vm, uint32_t irq, uint32_t operation)
-		enum irqstate irqstate)
 {
 	struct acrn_vpic *vpic;
 	struct i8259_reg_state *i8259;
@@ -478,43 +472,30 @@ static void vpic_set_irqstate(struct vm *vm, uint32_t irq,
 	}
 
 	spinlock_obtain(&(vpic->lock));
-	switch (irqstate) {
+	switch (operation) {
-	case IRQSTATE_ASSERT:
+	case GSI_SET_HIGH:
 		vpic_set_pinstate(vpic, pin, true);
 		break;
-	case IRQSTATE_DEASSERT:
+	case GSI_SET_LOW:
 		vpic_set_pinstate(vpic, pin, false);
 		break;
-	case IRQSTATE_PULSE:
+	case GSI_RAISING_PULSE:
 		vpic_set_pinstate(vpic, pin, true);
 		vpic_set_pinstate(vpic, pin, false);
 		break;
+	case GSI_FALLING_PULSE:
+		vpic_set_pinstate(vpic, pin, false);
+		vpic_set_pinstate(vpic, pin, true);
+		break;
 	default:
 		/*
 		 * The function caller could guarantee the pre condition.
-		 * All the possible 'irqstate' has been handled in prior cases.
 		 */
 		break;
 	}
 	spinlock_release(&(vpic->lock));
 }
 
-/* hypervisor interface: assert/deassert/pulse irq */
-void vpic_assert_irq(struct vm *vm, uint32_t irq)
-{
-	vpic_set_irqstate(vm, irq, IRQSTATE_ASSERT);
-}
-
-void vpic_deassert_irq(struct vm *vm, uint32_t irq)
-{
-	vpic_set_irqstate(vm, irq, IRQSTATE_DEASSERT);
-}
-
-void vpic_pulse_irq(struct vm *vm, uint32_t irq)
-{
-	vpic_set_irqstate(vm, irq, IRQSTATE_PULSE);
-}
-
 uint32_t
 vpic_pincount(void)
 {

hypervisor/include/arch/x86/guest/vioapic.h

@@ -52,9 +52,7 @@ void    vioapic_init(struct vm *vm);
 void	vioapic_cleanup(struct acrn_vioapic *vioapic);
 void	vioapic_reset(struct acrn_vioapic *vioapic);
 
-void	vioapic_assert_irq(struct vm *vm, uint32_t irq);
+void	vioapic_set_irq(struct vm *vm, uint32_t irq, uint32_t operation);
-void	vioapic_deassert_irq(struct vm *vm, uint32_t irq);
-void	vioapic_pulse_irq(struct vm *vm, uint32_t irq);
 void	vioapic_update_tmr(struct vcpu *vcpu);
 
 uint32_t	vioapic_pincount(struct vm *vm);

hypervisor/include/arch/x86/guest/vpic.h

@@ -121,9 +121,7 @@ struct acrn_vpic {
 
 void vpic_init(struct vm *vm);
 
-void vpic_assert_irq(struct vm *vm, uint32_t irq);
+void vpic_set_irq(struct vm *vm, uint32_t irq, uint32_t operation);
-void vpic_deassert_irq(struct vm *vm, uint32_t irq);
-void vpic_pulse_irq(struct vm *vm, uint32_t irq);
 
 void vpic_pending_intr(struct vm *vm, uint32_t *vecptr);
 void vpic_intr_accepted(struct vm *vm, uint32_t vector);