hv: vmsr: emulate IA32_FEATURE_CONTORL MSR for nested virtualization
In order to support nested virtualization, need to expose the "Enable VMX outside SMX operation" bit to L1 hypervisor. Tracked-On: #5923 Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -316,7 +316,7 @@ static void intercept_x2apic_msrs(uint8_t *msr_bitmap_arg, uint32_t mode)
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/**
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* @pre vcpu != NULL
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*/
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static void init_msr_area(struct acrn_vcpu *vcpu)
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static void prepare_auto_msr_area (struct acrn_vcpu *vcpu)
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{
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struct acrn_vm_config *cfg = get_vm_config(vcpu->vm->vm_id);
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uint16_t vcpu_clos = cfg->clos[vcpu->vcpu_id];
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@ -341,6 +341,27 @@ static void init_msr_area(struct acrn_vcpu *vcpu)
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}
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}
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/**
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* @pre vcpu != NULL
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*/
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void init_emulated_msrs(struct acrn_vcpu *vcpu)
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{
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uint64_t val64 = 0UL;
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/* MSR_IA32_FEATURE_CONTROL */
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if (is_nvmx_configured(vcpu->vm)) {
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/* currently support VMX outside SMX only */
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val64 |= MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX;
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}
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val64 |= MSR_IA32_FEATURE_CONTROL_LOCK;
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if (is_vsgx_supported(vcpu->vm->vm_id)) {
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val64 |= MSR_IA32_FEATURE_CONTROL_SGX_GE;
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}
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vcpu_set_guest_msr(vcpu, MSR_IA32_FEATURE_CONTROL, val64);
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}
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/**
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* @pre vcpu != NULL
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*/
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@ -379,7 +400,10 @@ void init_msr_emulation(struct acrn_vcpu *vcpu)
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pr_dbg("VMX_MSR_BITMAP: 0x%016lx ", value64);
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/* Initialize the MSR save/store area */
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init_msr_area(vcpu);
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prepare_auto_msr_area (vcpu);
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/* Setup initial value for emulated MSRs */
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init_emulated_msrs(vcpu);
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}
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static int32_t write_pat_msr(struct acrn_vcpu *vcpu, uint64_t value)
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@ -507,10 +531,7 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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}
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case MSR_IA32_FEATURE_CONTROL:
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{
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v = MSR_IA32_FEATURE_CONTROL_LOCK;
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if (is_vsgx_supported(vcpu->vm->vm_id)) {
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v |= MSR_IA32_FEATURE_CONTROL_SGX_GE;
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}
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v = vcpu_get_guest_msr(vcpu, MSR_IA32_FEATURE_CONTROL);
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break;
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}
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case MSR_IA32_MCG_CAP:
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