acrn-config: ehl: increase max msix table size and irte size

There are three TSN devices on EHL CRB, and each of them need 32
vectors.
In order to support TSN devices, increase msix table size and irte
size.

Tracked-On: #4831
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu 2020-05-24 07:54:36 +00:00 committed by wenlingz
parent 13e8e3c7f2
commit 957dc4e8d7
2 changed files with 4 additions and 4 deletions

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@ -55,8 +55,8 @@
<MAX_IOAPIC_NUM desc="Maximum number of IO-APICs.">1</MAX_IOAPIC_NUM>
<MAX_PCI_DEV_NUM desc="Maximum number of PCI devices.">96</MAX_PCI_DEV_NUM>
<MAX_IOAPIC_LINES desc="Maximum number of interrupt lines per IOAPIC.">120</MAX_IOAPIC_LINES>
<MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">64</MAX_PT_IRQ_ENTRIES>
<MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device.">16</MAX_MSIX_TABLE_NUM>
<MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">256</MAX_PT_IRQ_ENTRIES>
<MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device.">32</MAX_MSIX_TABLE_NUM>
<MAX_EMULATED_MMIO desc="Maximum number of emulated MMIO regions.">16</MAX_EMULATED_MMIO>
</CAPACITIES>
<MISC_CFG>

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@ -55,8 +55,8 @@
<MAX_IOAPIC_NUM desc="Maximum number of IO-APICs.">1</MAX_IOAPIC_NUM>
<MAX_PCI_DEV_NUM desc="Maximum number of PCI devices.">96</MAX_PCI_DEV_NUM>
<MAX_IOAPIC_LINES desc="Maximum number of interrupt lines per IOAPIC.">120</MAX_IOAPIC_LINES>
<MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">64</MAX_PT_IRQ_ENTRIES>
<MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device.">16</MAX_MSIX_TABLE_NUM>
<MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">256</MAX_PT_IRQ_ENTRIES>
<MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device.">32</MAX_MSIX_TABLE_NUM>
<MAX_EMULATED_MMIO desc="Maximum number of emulated MMIO regions.">16</MAX_EMULATED_MMIO>
</CAPACITIES>
<MISC_CFG>