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HV: Add MBA support in ACRN 

This patch adds RDT MBA support to detect, configure and
and setup MBA throttle registers based on VM configuration.

Tracked-On: #3725
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Vijay Dhanraj 2020-02-28 13:48:33 -08:00 committed by Eddie Dong
parent d54d35efe5
commit 92ee33b035
4 changed files with 100 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

97
hypervisor/arch/x86/rdt.c
View File

@ -19,21 +19,35 @@
static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
[RDT_RESOURCE_L3] = {
.bitmask = 0U,
.cbm_len = 0U,
.cache = {
.bitmask = 0U,
.cbm_len = 0U,
},
.clos_max = 0U,
.res_id = RDT_RESID_L3,
.msr_base = MSR_IA32_L3_MASK_BASE,
.platform_clos_array = NULL
},
[RDT_RESOURCE_L2] = {
.bitmask = 0U,
.cbm_len = 0U,
.cache = {
.bitmask = 0U,
.cbm_len = 0U,
},
.clos_max = 0U,
.res_id = RDT_RESID_L2,
.msr_base = MSR_IA32_L2_MASK_BASE,
.platform_clos_array = NULL
},
[RDT_RESOURCE_MBA] = {
.membw = {
.mba_max = 0U,
.delay_linear = true,
},
.clos_max = 0U,
.res_id = RDT_RESID_MBA,
.msr_base = MSR_IA32_MBA_MASK_BASE,
.platform_clos_array = NULL
},
};
const uint16_t hv_clos = 0U;
/* RDT features can support different numbers of CLOS. Set the lowers numerical
@ -53,9 +67,24 @@ static void rdt_read_cat_capability(int res)
* CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
*/
cpuid_subleaf(CPUID_RDT_ALLOCATION, res_cap_info[res].res_id, &eax, &ebx, &ecx, &edx);
res_cap_info[res].cbm_len = (uint16_t)((eax & 0xfU) + 1U);
res_cap_info[res].bitmask = ebx;
res_cap_info[res].clos_max = (uint16_t)(edx & 0xffffU) + 1;
res_cap_info[res].cache.cbm_len = (uint16_t)((eax & 0x1fU) + 1U);
res_cap_info[res].cache.bitmask = ebx;
res_cap_info[res].clos_max = (uint16_t)(edx & 0xffffU) + 1U;
}
static void rdt_read_mba_capability(int res)
{
uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
/* CPUID.(EAX=0x10,ECX=ResID):EAX[11:0] reports maximum MBA throttling value supported
* CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] reserved
* CPUID.(EAX=10H, ECX=ResID=3):ECX[2] reports if response of the delay values is linear
* CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
*/
cpuid_subleaf(CPUID_RDT_ALLOCATION, res_cap_info[res].res_id, &eax, &ebx, &ecx, &edx);
res_cap_info[res].membw.mba_max = (uint16_t)((eax & 0xfffU) + 1U);
res_cap_info[res].membw.delay_linear = ((ecx & 0x4U) != 0U) ? true : false;
res_cap_info[res].clos_max = (uint16_t)(edx & 0xffffU) + 1U;
}
int32_t init_rdt_cap_info(void)
@ -65,7 +94,7 @@ int32_t init_rdt_cap_info(void)
int32_t ret = 0;
if (pcpu_has_cap(X86_FEATURE_RDT_A)) {
cpuid_subleaf(CPUID_RDT_ALLOCATION, 0, &eax, &ebx, &ecx, &edx);
cpuid_subleaf(CPUID_RDT_ALLOCATION, 0U, &eax, &ebx, &ecx, &edx);
/* If HW supports L3 CAT, EBX[1] is set */
if ((ebx & 2U) != 0U) {
@ -77,6 +106,11 @@ int32_t init_rdt_cap_info(void)
rdt_read_cat_capability(RDT_RESOURCE_L2);
}
/* If HW supports MBA, EBX[3] is set */
if ((ebx & 8U) != 0U) {
rdt_read_mba_capability(RDT_RESOURCE_MBA);
}
for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
/* If clos_max == 0, the resource is not supported
* so skip checking and updating the clos_max
@ -93,6 +127,8 @@ int32_t init_rdt_cap_info(void)
res_cap_info[i].platform_clos_array = platform_l3_clos_array;
} else if (res_cap_info[i].res_id == RDT_RESID_L2) {
res_cap_info[i].platform_clos_array = platform_l2_clos_array;
} else if (res_cap_info[i].res_id == RDT_RESID_MBA) {
res_cap_info[i].platform_clos_array = platform_mba_clos_array;
} else {
res_cap_info[i].platform_clos_array = NULL;
}
@ -102,23 +138,49 @@ int32_t init_rdt_cap_info(void)
return ret;
}
static bool setup_res_clos_msr(uint16_t pcpu_id, struct platform_clos_info *res_clos_info)
/*
* @pre res < RDT_NUM_RESOURCES
*/
static bool setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_clos_info *res_clos_info)
{
bool ret = true;
uint16_t i;
uint32_t msr_index;
uint64_t val;
for (i = 0; i < platform_clos_num; i++) {
if ((fls32(res_clos_info->clos_mask) >= res_cap_info->cbm_len) ||
(res_clos_info->msr_index != (res_cap_info->msr_base + i))) {
for (i = 0U; i < platform_clos_num; i++) {
switch (res) {
case RDT_RESOURCE_L3:
case RDT_RESOURCE_L2:
if ((fls32(res_clos_info->clos_mask) >= res_cap_info[res].cache.cbm_len) ||
(res_clos_info->msr_index != (res_cap_info[res].msr_base + i))) {
ret = false;
pr_err("Fix CLOS %d mask=0x%x and(/or) MSR index=0x%x for Res_ID %d in board.c",
i, res_clos_info->clos_mask, res_clos_info->msr_index, res);
} else {
val = (uint64_t)res_clos_info->clos_mask;
}
break;
case RDT_RESOURCE_MBA:
if ((res_clos_info->mba_delay > res_cap_info[res].membw.mba_max) ||
(res_clos_info->msr_index != (res_cap_info[res].msr_base + i))) {
ret = false;
pr_err("Fix CLOS %d delay=0x%x and(/or) MSR index=0x%x for Res_ID %d in board.c",
i, res_clos_info->mba_delay, res_clos_info->msr_index, res);
} else {
val = (uint64_t)res_clos_info->mba_delay;
}
break;
default:
ret = false;
pr_err("Incorrect CLOS %d Mask=0x%x and(/or) MSR index=0x%x for Res_ID %d in board.c",
i, res_clos_info->clos_mask, res_clos_info->msr_index, res_cap_info[i].res_id);
ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res);
break;
}
if (!ret) {
break;
}
msr_index = res_clos_info->msr_index;
val = (uint64_t)res_clos_info->clos_mask;
msr_write_pcpu(msr_index, val, pcpu_id);
res_clos_info++;
}
@ -136,7 +198,7 @@ bool setup_clos(uint16_t pcpu_id)
* so skip setting up resource MSR.
*/
if (res_cap_info[i].clos_max > 0U) {
ret = setup_res_clos_msr(pcpu_id, res_cap_info[i].platform_clos_array);
ret = setup_res_clos_msr(pcpu_id, i, res_cap_info[i].platform_clos_array);
if (!ret)
break;
}
@ -172,7 +234,8 @@ bool is_platform_rdt_capable(void)
bool ret = false;
if ((res_cap_info[RDT_RESOURCE_L3].clos_max > 0U) ||
(res_cap_info[RDT_RESOURCE_L2].clos_max > 0U)) {
(res_cap_info[RDT_RESOURCE_L2].clos_max > 0U) ||
(res_cap_info[RDT_RESOURCE_MBA].clos_max > 0U)) {
ret = true;
}

2
hypervisor/include/arch/x86/board.h
View File

@ -15,6 +15,7 @@
struct acrn_vm;
struct platform_clos_info {
uint16_t mba_delay;
uint32_t clos_mask;
uint32_t msr_index;
};
@ -24,6 +25,7 @@ extern struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
extern struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
extern struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
extern struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
extern const struct cpu_state_table board_cpu_state_tbl;

1
hypervisor/include/arch/x86/msr.h
View File

@ -341,6 +341,7 @@
#define MSR_IA32_PM_CTL1 0x00000DB1U
#define MSR_IA32_THREAD_STALL 0x00000DB2U
#define MSR_IA32_L2_MASK_BASE 0x00000D10U
#define MSR_IA32_MBA_MASK_BASE 0x00000D50U
#define MSR_IA32_BNDCFGS 0x00000D90U
#define MSR_IA32_EFER 0xC0000080U
#define MSR_IA32_STAR 0xC0000081U

21
hypervisor/include/arch/x86/rdt.h
View File

@ -10,21 +10,34 @@
enum {
RDT_RESOURCE_L3,
RDT_RESOURCE_L2,
RDT_RESOURCE_MBA,
/* Must be the last */
RDT_NUM_RESOURCES,
};
#define RDT_RESID_L3 1U
#define RDT_RESID_L2 2U
#define RDT_RESID_L3 1U
#define RDT_RESID_L2 2U
#define RDT_RESID_MBA 3U
extern const uint16_t hv_clos;
extern const uint16_t platform_clos_num;
struct rdt_cache {
uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way
may be used by other entities in the platform (e.g. GPU) */
uint16_t cbm_len; /* Length of Cache mask in bits */
};
struct rdt_membw {
uint16_t mba_max; /* Max MBA delay throttling value supported */
bool delay_linear; /* True if memory B/W delay is in linear scale */
};
/* The intel Resource Director Tech(RDT) based Allocation Tech support */
struct rdt_info {
uint32_t bitmask; /* Shared CLOS bitmask used by other entities */
uint16_t cbm_len; /* Length of Cache mask in bits */
struct rdt_cache cache;
struct rdt_membw membw;
uint16_t clos_max; /* Maximum CLOS supported, 0 indicates resource is not supported.*/
uint32_t res_id;
uint32_t msr_base; /* MSR base to program clos mask*/