HV: vuart: split vuart_write
Split vuart_write as its cyclomatic complexity is greater than 20. Tracked-On: #2987 Signed-off-by: Conghui Chen <conghui.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Conghui Chen
wenlingz
parent
14e2c66a1e
commit
926fe655d5
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@ -218,6 +218,119 @@ static uint8_t get_modem_status(uint8_t mcr)
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return msr;
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return msr;
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}
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}
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static uint8_t update_modem_status(uint8_t new_msr, uint8_t old_msr)
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{
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uint8_t update_msr = old_msr;
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/*
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* Detect if there has been any change between the
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* previous and the new value of MSR. If there is
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* then assert the appropriate MSR delta bit.
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*/
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if (((new_msr & MSR_CTS) ^ (old_msr & MSR_CTS)) != 0U) {
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update_msr |= MSR_DCTS;
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}
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if (((new_msr & MSR_DSR) ^ (old_msr & MSR_DSR)) != 0U) {
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update_msr |= MSR_DDSR;
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}
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if (((new_msr & MSR_DCD) ^ (old_msr & MSR_DCD)) != 0U) {
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update_msr |= MSR_DDCD;
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}
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if (((new_msr & MSR_RI) == 0U) && ((old_msr & MSR_RI) != 0U)) {
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update_msr |= MSR_TERI;
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}
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update_msr &= MSR_DELTA_MASK;
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update_msr |= new_msr;
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return update_msr;
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}
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/*
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* @pre: vu != NULL
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*/
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static void write_reg(struct acrn_vuart *vu, uint16_t reg, uint8_t value_u8)
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{
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uint8_t msr;
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vuart_lock(vu);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if (((vu->lcr & LCR_DLAB) != 0U) && (reg == UART16550_DLL)) {
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vu->dll = value_u8;
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} else if (((vu->lcr & LCR_DLAB) != 0U) && (reg == UART16550_DLM)) {
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vu->dlh = value_u8;
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} else {
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switch (reg) {
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case UART16550_THR:
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if ((vu->mcr & MCR_LOOPBACK) != 0U) {
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fifo_putchar(&vu->rxfifo, (char)value_u8);
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vu->lsr |= LSR_OE;
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} else {
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fifo_putchar(&vu->txfifo, (char)value_u8);
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}
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vu->thre_int_pending = true;
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break;
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case UART16550_IER:
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/*
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* Apply mask so that bits 4-7 are 0
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* Also enables bits 0-3 only if they're 1
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*/
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vu->ier = value_u8 & 0x0FU;
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break;
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case UART16550_FCR:
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/*
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* The FCR_ENABLE bit must be '1' for the programming
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* of other FCR bits to be effective.
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*/
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if ((value_u8 & FCR_FIFOE) == 0U) {
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vu->fcr = 0U;
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} else {
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if ((value_u8 & FCR_RFR) != 0U) {
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fifo_reset(&vu->rxfifo);
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}
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vu->fcr = value_u8 & (FCR_FIFOE | FCR_DMA | FCR_RX_MASK);
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}
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break;
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case UART16550_LCR:
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vu->lcr = value_u8;
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break;
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case UART16550_MCR:
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/* Apply mask so that bits 5-7 are 0 */
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vu->mcr = value_u8 & 0x1FU;
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msr = get_modem_status(vu->mcr);
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/*
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* Update the value of MSR while retaining the delta
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* bits.
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*/
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vu->msr = update_modem_status(msr, vu->msr);
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break;
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case UART16550_LSR:
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/*
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* Line status register is not meant to be written to
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* during normal operation.
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*/
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break;
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case UART16550_MSR:
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/*
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* As far as I can tell MSR is a read-only register.
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*/
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break;
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case UART16550_SCR:
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vu->scr = value_u8;
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break;
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default:
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/*
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* For the reg that is not handled (either a read-only
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* register or an invalid register), ignore the write to it.
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* Gracefully return if prior case clauses have not been met.
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*/
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break;
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}
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}
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vuart_toggle_intr(vu);
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vuart_unlock(vu);
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}
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static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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__unused size_t width, uint32_t value)
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__unused size_t width, uint32_t value)
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{
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{
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@ -225,7 +338,6 @@ static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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struct acrn_vuart *vu = find_vuart_by_port(vm, offset);
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struct acrn_vuart *vu = find_vuart_by_port(vm, offset);
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uint8_t value_u8 = (uint8_t)value;
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uint8_t value_u8 = (uint8_t)value;
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struct acrn_vuart *target_vu = NULL;
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struct acrn_vuart *target_vu = NULL;
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uint8_t msr;
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if (vu != NULL) {
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if (vu != NULL) {
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offset -= vu->port_base;
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offset -= vu->port_base;
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@ -235,100 +347,7 @@ static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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(offset == UART16550_THR) && (target_vu != NULL)) {
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(offset == UART16550_THR) && (target_vu != NULL)) {
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send_to_target(target_vu, value_u8);
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send_to_target(target_vu, value_u8);
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} else {
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} else {
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vuart_lock(vu);
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write_reg(vu, offset, value_u8);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((vu->lcr & LCR_DLAB) != 0U && offset == UART16550_DLL) {
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vu->dll = value_u8;
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} else if ((vu->lcr & LCR_DLAB) != 0U && offset == UART16550_DLM) {
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vu->dlh = value_u8;
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} else {
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switch (offset) {
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case UART16550_THR:
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if (vu->mcr & MCR_LOOPBACK) {
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fifo_putchar(&vu->rxfifo, (char)value_u8);
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vu->lsr |= LSR_OE;
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} else {
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fifo_putchar(&vu->txfifo, (char)value_u8);
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}
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vu->thre_int_pending = true;
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break;
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case UART16550_IER:
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/*
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* Apply mask so that bits 4-7 are 0
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* Also enables bits 0-3 only if they're 1
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*/
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vu->ier = value_u8 & 0x0FU;
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break;
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case UART16550_FCR:
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/*
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* The FCR_ENABLE bit must be '1' for the programming
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* of other FCR bits to be effective.
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*/
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if ((value_u8 & FCR_FIFOE) == 0U) {
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vu->fcr = 0U;
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} else {
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if ((value_u8 & FCR_RFR) != 0U) {
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fifo_reset(&vu->rxfifo);
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}
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vu->fcr = value_u8 & (FCR_FIFOE | FCR_DMA | FCR_RX_MASK);
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}
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break;
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case UART16550_LCR:
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vu->lcr = value_u8;
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break;
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case UART16550_MCR:
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/* Apply mask so that bits 5-7 are 0 */
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vu->mcr = value & 0x1F;
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msr = get_modem_status(vu->mcr);
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/*
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* Detect if there has been any change between the
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* previous and the new value of MSR. If there is
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* then assert the appropriate MSR delta bit.
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*/
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if ((msr & MSR_CTS) ^ (vu->msr & MSR_CTS))
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vu->msr |= MSR_DCTS;
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if ((msr & MSR_DSR) ^ (vu->msr & MSR_DSR))
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vu->msr |= MSR_DDSR;
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if ((msr & MSR_DCD) ^ (vu->msr & MSR_DCD))
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vu->msr |= MSR_DDCD;
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if ((vu->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
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vu->msr |= MSR_TERI;
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/*
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* Update the value of MSR while retaining the delta
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* bits.
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*/
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vu->msr &= MSR_DELTA_MASK;
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vu->msr |= msr;
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break;
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case UART16550_LSR:
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/*
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* Line status register is not meant to be written to
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* during normal operation.
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*/
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break;
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case UART16550_MSR:
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/*
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* As far as I can tell MSR is a read-only register.
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*/
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break;
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case UART16550_SCR:
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vu->scr = value_u8;
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break;
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default:
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/*
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* For the offset that is not handled (either a read-only
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* register or an invalid register), ignore the write to it.
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* Gracefully return if prior case clauses have not been met.
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*/
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break;
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}
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}
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vuart_toggle_intr(vu);
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vuart_unlock(vu);
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}
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}
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}
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}
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return true;
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return true;
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