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hv: fix mapping between GSI Num#2 and PIC IRQ #0 

route GSI number#2 to PIC IRQ#0, as by default IRQ for
 8254 timer is connected to I/O APIC Pin #2 and PIC Pin #0

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yonghua Huang 2018-10-25 01:55:35 +08:00 committed by wenlingz
parent 96f8becca6
commit 8f7fa50d5a
1 changed files with 8 additions and 2 deletions
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10
hypervisor/common/hypercall.c
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@ -336,6 +336,7 @@ int32_t hcall_set_vcpu_regs(struct vm *vm, uint16_t vmid, uint64_t param)
int32_t hcall_set_irqline(const struct vm *vm, uint16_t vmid,
struct acrn_irqline_ops *ops)
{
uint32_t irq_pic;
struct vm *target_vm = get_vm_from_vmid(vmid);
if (target_vm == NULL) {
@ -347,8 +348,13 @@ int32_t hcall_set_irqline(const struct vm *vm, uint16_t vmid,
}
if (ops->nr_gsi < vpic_pincount()) {
/* Call vpic for pic injection */
vpic_set_irq(target_vm, ops->nr_gsi, ops->op);
/*
* IRQ line for 8254 timer is connected to
* I/O APIC pin #2 but PIC pin #0,route GSI
* number #2 to PIC IRQ #0.
*/
irq_pic = (ops->nr_gsi == 2U) ? 0U : ops->nr_gsi;
vpic_set_irq(target_vm, irq_pic, ops->op);
}
/* handle IOAPIC irqline */