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hv: vuart bugfix for additional byte in tx fifo 

For communication vuart, when it send data to target vuart's fifo, it
should meet the conditions:

1. MCR_LOOPBACK is not set
2. LCR_DLAB is not set
3. access reg is UART16550_THR
4. target_vu is not null

But the LCR_DLAB is missed now, and when vuart set it's UART16550_DLL,
it will be send to target by mistake as UART16550_DLL = UART16550_THR.
Add the missed condition.

DLAB in uart16550 spec:

Divisor Latch Access Bit.
1 = Allows access to the Divisor Latch Registers and reading of the FIFO
Control Register.
0 = Allows access to RBR, THR, IER and IIR registers.

Tracked-On: #3681
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Conghui Chen 2019-08-13 13:02:39 +00:00 committed by wenlingz
parent d3e564334a
commit 8e4e1c96d1
1 changed files with 2 additions and 2 deletions
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4
hypervisor/dm/vuart.c
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@ -356,8 +356,8 @@ static bool vuart_write(struct acrn_vcpu *vcpu, uint16_t offset_arg,
offset -= vu->port_base; offset -= vu->port_base;
target_vu = vu->target_vu; target_vu = vu->target_vu;
if (((vu->mcr & MCR_LOOPBACK) == 0U) && if (((vu->mcr & MCR_LOOPBACK) == 0U) && ((vu->lcr & LCR_DLAB) == 0U)
(offset == UART16550_THR) && (target_vu != NULL)) { && (offset == UART16550_THR) && (target_vu != NULL)) {
send_to_target(target_vu, value_u8); send_to_target(target_vu, value_u8);
vuart_lock(vu, rflags); vuart_lock(vu, rflags);
vu->thre_int_pending = true; vu->thre_int_pending = true;