doc: Fix links
- Fix broken software.intel.com links that moved to intel.com domain Signed-off-by: Reyes, Amy <amy.reyes@intel.com>
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@ -838,4 +838,4 @@ sequence defined in System V Application Binary Interface AMD64 Architecture
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Processor Supplement.
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Refer to the `System V Application Binary Interface AMD64 Architecture Processor Supplement <https://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf>`_.
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Refer to the `System V Application Binary Interface AMD64 Architecture Processor Supplement <https://www.intel.com/content/dam/develop/external/us/en/documents/mpx-linux64-abi.pdf>`_.
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@ -32,7 +32,7 @@ ways:
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This atomic operation is called a Split-locked Access. For this situation,
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the LOCK# bus signal is asserted to lock the system bus, to ensure
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the operation is atomic. See `Intel 64 and IA-32 Architectures Software Developer's Manual(SDM), Volume 3, (Section 8.1.2 Bus Locking) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_.
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the operation is atomic. See `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3, (Section 8.1.2 Bus Locking) <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
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Split-locked Access can cause unexpected long latency to ordinary memory
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operations by other CPUs while the bus is locked. This degraded system
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@ -51,9 +51,7 @@ an opportunity to decide how to handle this instruction:
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- It can allow the instruction to run with LOCK# bus signal potentially
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impacting performance of other CPUs.
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- It can disable LOCK# assertion for split locked access, but
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improperly makes the instruction non-atomic. (Intel plans to remove this CPU feature
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from upcoming products as documented in
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`SDM, Volume 1, (Section 2.4 PROPOSED REMOVAL FROM UPCOMING PRODUCTS.) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-1-basic-architecture>`_
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improperly makes the instruction non-atomic.
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- It can terminate the software at this instruction.
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Feature Enumeration and Control
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@ -11,7 +11,7 @@ resources, ACRN can optimize RTVM performance over regular VMs. In ACRN, the
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CAT and MBA are configured via the "VM-Configuration". The resources
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allocated for VMs are determined in the VM configuration (:ref:`rdt_vm_configuration`).
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For further details on the Intel RDT, refer to `Intel 64 and IA-32 Architectures Software Developer's Manual, (Section 17.19 Intel Resource Director Technology Allocation Features) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_.
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For further details on the Intel RDT, refer to `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3, (Section 17.19 Intel Resource Director Technology Allocation Features) <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
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Objective of CAT
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@ -9,7 +9,7 @@ Overview
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Refer to `Intel Analysis of L1TF`_ and `Linux L1TF document`_ for details.
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.. _Intel Analysis of L1TF:
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https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1-terminal-fault
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https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/l1-terminal-fault.html
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.. _Linux L1TF document:
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https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html
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@ -130,15 +130,15 @@ providing necessary capability for VMM to use for further mitigation.
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ACRN will check the platform capability based on `CPUID enumeration
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and architectural MSR`_. For an L1TF affected platform (CPUID.07H.EDX.29
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with MSR_IA32_ARCH_CAPABILITIES), L1D_FLUSH capability(CPUID.07H.EDX.28)
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with MSR_IA32_ARCH_CAPABILITIES), L1D_FLUSH capability (CPUID.07H.EDX.28)
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must be supported.
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.. _CPUID enumeration and architectural MSR:
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https://software.intel.com/security-software-guidance/insights/deep-dive-cpuid-enumeration-and-architectural-msrs
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https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html
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Not all the mitigations below will be implemented in ACRN, and not all of
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them apply to a specific ACRN deployment. Check the 'Mitigation Status'_ and
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'Mitigation Recommendations'_ sections for guidance.
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them apply to a specific ACRN deployment. Check the `Mitigation Status`_ and
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`Mitigation Recommendations`_ sections for guidance.
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L1D Flush on VMENTRY
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====================
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@ -28,10 +28,10 @@ Steps #2 and #3 configure RDT resources for a VM and can be done in two ways:
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The following sections discuss how to detect, enumerate capabilities, and
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configure RDT resources for VMs in the ACRN hypervisor.
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For further details, refer to the ACRN RDT high-level design
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:ref:`hv_rdt` and `Intel 64 and IA-32 Architectures Software Developer's
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Manual, (Section 17.19 Intel Resource Director Technology Allocation Features)
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<https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_
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For further details, refer to the ACRN RDT high-level design :ref:`hv_rdt` and
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`Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3,
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(Section 17.19 Intel Resource Director Technology Allocation Features)
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<https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
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.. _rdt_detection_capabilities:
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@ -72,11 +72,11 @@ using LAPIC passthrough. A few exceptions exist:
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- NMI - ACRN uses NMI for system-level notification.
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You should avoid VM-exits triggered by operations initiated by the
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vCPU. Refer to the `Intel Software Developer Manuals (SDM)
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<https://software.intel.com/en-us/articles/intel-sdm>`_ "Instructions
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Cause VM-exits Unconditionally" (SDM V3, 25.1.2) and "Instructions That
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Cause VM-exits Conditionally" (SDM V3, 25.1.3).
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You should avoid VM-exits triggered by operations initiated by the vCPU. Refer
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to the `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM)
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<https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_
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"Instructions That Cause VM Exits Unconditionally" (SDM V3, 25.1.2) and
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"Instructions That Cause VM Exits Conditionally" (SDM V3, 25.1.3).
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Tip: Do not use CPUID in a real-time critical section.
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The CPUID instruction causes VM-exits unconditionally. You should
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