doc: Fix links

- Fix broken software.intel.com links that moved to intel.com domain

Signed-off-by: Reyes, Amy <amy.reyes@intel.com>

doc/developer-guides/asm_coding_guidelines.rst

@@ -838,4 +838,4 @@ sequence defined in System V Application Binary Interface AMD64 Architecture
 Processor Supplement.
 
 
-Refer to the `System V Application Binary Interface AMD64 Architecture Processor Supplement <https://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf>`_.
+Refer to the `System V Application Binary Interface AMD64 Architecture Processor Supplement <https://www.intel.com/content/dam/develop/external/us/en/documents/mpx-linux64-abi.pdf>`_.

doc/developer-guides/hld/hld-splitlock.rst

@@ -32,7 +32,7 @@ ways:
 
    This atomic operation is called a Split-locked Access. For this situation,
    the LOCK# bus signal is asserted to lock the system bus, to ensure
-   the operation is atomic. See `Intel 64 and IA-32 Architectures Software Developer's Manual(SDM), Volume 3, (Section 8.1.2 Bus Locking) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_.
+   the operation is atomic. See `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3, (Section 8.1.2 Bus Locking) <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
 
 Split-locked Access can cause unexpected long latency to ordinary memory
 operations by other CPUs while the bus is locked. This degraded system
@@ -51,9 +51,7 @@ an opportunity to decide how to handle this instruction:
 - It can allow the instruction to run with LOCK# bus signal potentially
   impacting performance of other CPUs.
 - It can disable LOCK# assertion for split locked access, but
-  improperly makes the instruction non-atomic. (Intel plans to remove this CPU feature
-  from upcoming products as documented in
-  `SDM, Volume 1, (Section 2.4 PROPOSED REMOVAL FROM UPCOMING PRODUCTS.) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-1-basic-architecture>`_
+  improperly makes the instruction non-atomic.
 - It can terminate the software at this instruction.
 
 Feature Enumeration and Control

doc/developer-guides/hld/hv-rdt.rst

@@ -11,7 +11,7 @@ resources, ACRN can optimize RTVM performance over regular VMs. In ACRN, the
 CAT and MBA are configured via the "VM-Configuration". The resources
 allocated for VMs are determined in the VM configuration (:ref:`rdt_vm_configuration`).
 
-For further details on the Intel RDT, refer to `Intel 64 and IA-32 Architectures Software Developer's Manual, (Section 17.19 Intel Resource Director Technology Allocation Features) <https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_.
+For further details on the Intel RDT, refer to `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3, (Section 17.19 Intel Resource Director Technology Allocation Features) <https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
 
 
 Objective of CAT

doc/developer-guides/l1tf.rst

@@ -9,7 +9,7 @@ Overview
 Refer to `Intel Analysis of L1TF`_ and `Linux L1TF document`_ for details.
 
 .. _Intel Analysis of L1TF:
-   https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-l1-terminal-fault
+   https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/l1-terminal-fault.html
 
 .. _Linux L1TF document:
    https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html
@@ -130,15 +130,15 @@ providing necessary capability for VMM to use for further mitigation.
 
 ACRN will check the platform capability based on `CPUID enumeration
 and architectural MSR`_. For an L1TF affected platform (CPUID.07H.EDX.29
-with MSR_IA32_ARCH_CAPABILITIES), L1D_FLUSH capability(CPUID.07H.EDX.28)
+with MSR_IA32_ARCH_CAPABILITIES), L1D_FLUSH capability (CPUID.07H.EDX.28)
 must be supported.
 
 .. _CPUID enumeration and architectural MSR:
-   https://software.intel.com/security-software-guidance/insights/deep-dive-cpuid-enumeration-and-architectural-msrs
+   https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html
 
 Not all the mitigations below will be implemented in ACRN, and not all of
-them apply to a specific ACRN deployment. Check the 'Mitigation Status'_ and
-'Mitigation Recommendations'_ sections for guidance.
+them apply to a specific ACRN deployment. Check the `Mitigation Status`_ and
+`Mitigation Recommendations`_ sections for guidance.
 
 L1D Flush on VMENTRY
 ====================

doc/tutorials/rdt_configuration.rst

@@ -28,10 +28,10 @@ Steps #2 and #3 configure RDT resources for a VM and can be done in two ways:
 The following sections discuss how to detect, enumerate capabilities, and
 configure RDT resources for VMs in the ACRN hypervisor.
 
-For further details, refer to the ACRN RDT high-level design
-:ref:`hv_rdt` and `Intel 64 and IA-32 Architectures Software Developer's
-Manual, (Section 17.19 Intel Resource Director Technology Allocation Features)
-<https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_
+For further details, refer to the ACRN RDT high-level design :ref:`hv_rdt` and
+`Intel 64 and IA-32 Architectures Software Developer's Manual (SDM), Volume 3,
+(Section 17.19 Intel Resource Director Technology Allocation Features)
+<https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_.
 
 .. _rdt_detection_capabilities:
 

doc/tutorials/rtvm_performance_tips.rst

@@ -72,11 +72,11 @@ using LAPIC passthrough. A few exceptions exist:
 
 - NMI - ACRN uses NMI for system-level notification.
 
-You should avoid VM-exits triggered by operations initiated by the
-vCPU. Refer to the `Intel Software Developer Manuals (SDM)
-<https://software.intel.com/en-us/articles/intel-sdm>`_ "Instructions
-Cause VM-exits Unconditionally" (SDM V3, 25.1.2) and "Instructions That
-Cause VM-exits Conditionally" (SDM V3, 25.1.3).
+You should avoid VM-exits triggered by operations initiated by the vCPU. Refer
+to the `Intel 64 and IA-32 Architectures Software Developer's Manual (SDM)
+<https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html>`_
+"Instructions That Cause VM Exits Unconditionally" (SDM V3, 25.1.2) and
+"Instructions That Cause VM Exits Conditionally" (SDM V3, 25.1.3).
 
 Tip: Do not use CPUID in a real-time critical section.
    The CPUID instruction causes VM-exits unconditionally. You should