mmu: refine function check_mmu_1gb_support
change its input from map_params to page_table_type, and make it as a public API. Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Xu, Anthony <anthony.xu@intel.com>
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4f6bdee0c5
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@ -124,11 +124,11 @@ void invept(struct vcpu *vcpu)
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_invept(INVEPT_TYPE_ALL_CONTEXTS, desc);
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_invept(INVEPT_TYPE_ALL_CONTEXTS, desc);
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}
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}
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static bool check_mmu_1gb_support(struct map_params *map_params)
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bool check_mmu_1gb_support(int page_table_type)
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{
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{
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bool status = false;
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bool status = false;
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if (map_params->page_table_type == PTT_EPT)
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if (page_table_type == PTT_EPT)
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status = cpu_has_vmx_ept_cap(VMX_EPT_1GB_PAGE);
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status = cpu_has_vmx_ept_cap(VMX_EPT_1GB_PAGE);
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else
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else
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status = cpu_has_cap(X86_FEATURE_PAGE1GB);
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status = cpu_has_cap(X86_FEATURE_PAGE1GB);
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@ -656,7 +656,8 @@ int obtain_last_page_table_entry(struct map_params *map_params,
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entry->entry_level = IA32E_PML4;
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entry->entry_level = IA32E_PML4;
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entry->entry_base = table_addr;
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entry->entry_base = table_addr;
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entry->entry_present = PT_NOT_PRESENT;
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entry->entry_present = PT_NOT_PRESENT;
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entry->page_size = check_mmu_1gb_support(map_params) ?
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entry->page_size =
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check_mmu_1gb_support(map_params->page_table_type) ?
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(PAGE_SIZE_1G) : (PAGE_SIZE_2M);
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(PAGE_SIZE_1G) : (PAGE_SIZE_2M);
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entry->entry_off = fetch_page_table_offset(addr, IA32E_PML4);
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entry->entry_off = fetch_page_table_offset(addr, IA32E_PML4);
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entry->entry_val = table_entry;
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entry->entry_val = table_entry;
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@ -678,7 +679,8 @@ int obtain_last_page_table_entry(struct map_params *map_params,
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entry->entry_level = IA32E_PDPT;
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entry->entry_level = IA32E_PDPT;
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entry->entry_base = table_addr;
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entry->entry_base = table_addr;
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entry->entry_present = PT_NOT_PRESENT;
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entry->entry_present = PT_NOT_PRESENT;
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entry->page_size = check_mmu_1gb_support(map_params) ?
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entry->page_size =
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check_mmu_1gb_support(map_params->page_table_type) ?
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(PAGE_SIZE_1G) : (PAGE_SIZE_2M);
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(PAGE_SIZE_1G) : (PAGE_SIZE_2M);
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entry->entry_off = fetch_page_table_offset(addr, IA32E_PDPT);
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entry->entry_off = fetch_page_table_offset(addr, IA32E_PDPT);
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entry->entry_val = table_entry;
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entry->entry_val = table_entry;
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@ -688,7 +690,8 @@ int obtain_last_page_table_entry(struct map_params *map_params,
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/* 1GB page size, return the base addr of the pg entry*/
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/* 1GB page size, return the base addr of the pg entry*/
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entry->entry_level = IA32E_PDPT;
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entry->entry_level = IA32E_PDPT;
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entry->entry_base = table_addr;
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entry->entry_base = table_addr;
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entry->page_size = check_mmu_1gb_support(map_params) ?
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entry->page_size =
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check_mmu_1gb_support(map_params->page_table_type) ?
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(PAGE_SIZE_1G) : (PAGE_SIZE_2M);
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(PAGE_SIZE_1G) : (PAGE_SIZE_2M);
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entry->entry_present = PT_PRESENT;
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entry->entry_present = PT_PRESENT;
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entry->entry_off = fetch_page_table_offset(addr, IA32E_PDPT);
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entry->entry_off = fetch_page_table_offset(addr, IA32E_PDPT);
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@ -769,7 +772,7 @@ static uint64_t update_page_table_entry(struct map_params *map_params,
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if ((remaining_size >= MEM_1G)
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if ((remaining_size >= MEM_1G)
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&& (MEM_ALIGNED_CHECK(vaddr, MEM_1G))
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&& (MEM_ALIGNED_CHECK(vaddr, MEM_1G))
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&& (MEM_ALIGNED_CHECK(paddr, MEM_1G))
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&& (MEM_ALIGNED_CHECK(paddr, MEM_1G))
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&& check_mmu_1gb_support(map_params)) {
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&& check_mmu_1gb_support(map_params->page_table_type)) {
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/* Map this 1 GByte memory region */
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/* Map this 1 GByte memory region */
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adjustment_size = map_mem_region(vaddr, paddr,
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adjustment_size = map_mem_region(vaddr, paddr,
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table_addr, attr, IA32E_PDPT,
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table_addr, attr, IA32E_PDPT,
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@ -315,6 +315,7 @@ struct mem_io_node {
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};
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};
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uint64_t get_paging_pml4(void);
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uint64_t get_paging_pml4(void);
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bool check_mmu_1gb_support(int page_table_type);
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void *alloc_paging_struct(void);
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void *alloc_paging_struct(void);
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void free_paging_struct(void *ptr);
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void free_paging_struct(void *ptr);
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void enable_paging(uint64_t pml4_base_addr);
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void enable_paging(uint64_t pml4_base_addr);
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