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acrn-hypervisor
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HV: remove bar info in vm description 

We have enabled bar decoding in init ptdev, so hard-coded bar info is not needed
any more.

Tracked-On: #2431
Signed-off-by: Victor Sun <victor.sun@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Victor Sun 2019-01-18 01:20:27 +08:00 committed by ACRN System Integration
parent f082176df0
commit 69d883560a
2 changed files with 1 additions and 172 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
hypervisor/partition/apl-mrb/vm_description.c
View File

@ -14,7 +14,6 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
{/*vdev 0: hostbridge */
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
.ops = &pci_ops_vdev_hostbridge,
.bar = {},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
}
@ -23,42 +22,8 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
{/*vdev 1: SATA controller*/
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[1] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x0U},
.bar = {
[0] = {
.base = 0xb3f10000UL,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[1] = {
.base = 0xb3f53000UL,
.size = 0x100UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0xb3f52000UL,
.size = 0x800UL,
.type = PCIBAR_MEM32
},
}
}
},
}
@ -71,7 +36,6 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
{/*vdev 0: hostbridge*/
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
.ops = &pci_ops_vdev_hostbridge,
.bar = {},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
}
@ -80,54 +44,16 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
{/*vdev 1: USB controller*/
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x10000UL,
.type = PCIBAR_MEM32
},
},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x0U},
.bar = {
[0] = {
.base = 0xb3f00000UL,
.size = 0x10000UL,
.type = PCIBAR_MEM64
},
}
}
},
{/*vdev 2: Ethernet*/
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x80000UL,
.type = PCIBAR_MEM32
},
[3] = {
.base = 0UL,
.size = 0x4000UL,
.type = PCIBAR_MEM32
},
},
.pdev = {
.bdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x0U},
.bar = {
[0] = {
.base = 0xb3c00000UL,
.size = 0x80000UL,
.type = PCIBAR_MEM32
},
[3] = {
.base = 0xb3c80000UL,
.size = 0x4000UL,
.type = PCIBAR_MEM32
},
}
}
},
}

99
hypervisor/partition/dnv-cb2/vm_description.c
View File

@ -13,7 +13,6 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
{/*vdev 0: hostbridge */
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
.ops = &pci_ops_vdev_hostbridge,
.bar = {},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
}
@ -22,54 +21,17 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
{/*vdev 1: Ethernet*/
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x200000UL,
.type = PCIBAR_MEM32,
},
[4] = {
.base = 0UL,
.size = 0x4000UL,
.type = PCIBAR_MEM32,
},
},
.pdev = {
.bdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x1U},
.bar = {
[0] = {
.base = 0x80C00000,
.size = 0x200000UL,
.type = PCIBAR_MEM32,
},
[4] = {
.base = 0x81000000,
.size = 0x4000UL,
.type = PCIBAR_MEM32,
},
}
}
},
{/*vdev 2: USB*/
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x10000UL,
.type = PCIBAR_MEM32,
}
},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x0U},
.bar = {
[0] = {
.base = 0x81340000,
.size = 0x10000UL,
.type = PCIBAR_MEM32,
}
}
}
},
}
@ -82,7 +44,6 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
{/*vdev 0: hostbridge*/
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
.ops = &pci_ops_vdev_hostbridge,
.bar = {},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
}
@ -91,75 +52,17 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
{/*vdev 1: SATA controller*/
.vbdf.bits = {.b = 0x00U, .d = 0x05U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[1] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x0U},
.bar = {
[0] = {
.base = 0x81354000,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[1] = {
.base = 0x8135f000,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0x8135e000,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
}
}
},
{/*vdev 2: Ethernet*/
.vbdf.bits = {.b = 0x00U, .d = 0x06U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x200000UL,
.type = PCIBAR_MEM32,
},
[4] = {
.base = 0UL,
.size = 0x4000UL,
.type = PCIBAR_MEM32,
},
},
.pdev = {
.bdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x0U},
.bar = {
[0] = {
.base = 0x80e00000,
.size = 0x200000UL,
.type = PCIBAR_MEM32,
},
[4] = {
.base = 0x81004000,
.size = 0x4000UL,
.type = PCIBAR_MEM32,
}
}
}
},