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hv: apicv: remove APIC_OFFSET_SELF_IPI(0x3F0) register 

From SDM Vol3 Table 10-1 Local APIC Register Address Map. The 0x3F0 is
reserved.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yu Wang 2018-08-15 01:13:21 +00:00 committed by wenlingz
parent 93f91268c9
commit 604b5a454b
2 changed files with 0 additions and 10 deletions
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9
hypervisor/arch/x86/guest/vlapic.c
View File

@ -1431,12 +1431,6 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
case APIC_OFFSET_TIMER_DCR:
*data = lapic->dcr_timer;
break;
case APIC_OFFSET_SELF_IPI:
/*
* XXX generate a GP fault if vlapic is in x2apic mode
*/
*data = 0UL;
break;
case APIC_OFFSET_RRR:
default:
*data = 0UL;
@ -1527,9 +1521,6 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
vlapic_esr_write_handler(vlapic);
break;
case APIC_OFFSET_SELF_IPI:
break;
case APIC_OFFSET_VER:
case APIC_OFFSET_APR:
case APIC_OFFSET_PPR:

1
hypervisor/arch/x86/guest/vlapic_priv.h
View File

@ -80,7 +80,6 @@
#define APIC_OFFSET_TIMER_ICR 0x380U /* Timer's Initial Count */
#define APIC_OFFSET_TIMER_CCR 0x390U /* Timer's Current Count */
#define APIC_OFFSET_TIMER_DCR 0x3E0U /* Timer's Divide Configuration */
#define APIC_OFFSET_SELF_IPI 0x3F0U /* Self IPI register */
/*
* 16 priority levels with at most one vector injected per level.