hv: apicv: remove APIC_OFFSET_SELF_IPI(0x3F0) register
From SDM Vol3 Table 10-1 Local APIC Register Address Map. The 0x3F0 is reserved. Signed-off-by: Yu Wang <yu1.wang@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
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@ -1431,12 +1431,6 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
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case APIC_OFFSET_TIMER_DCR:
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*data = lapic->dcr_timer;
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break;
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case APIC_OFFSET_SELF_IPI:
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/*
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* XXX generate a GP fault if vlapic is in x2apic mode
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*/
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*data = 0UL;
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break;
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case APIC_OFFSET_RRR:
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default:
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*data = 0UL;
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@ -1527,9 +1521,6 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
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vlapic_esr_write_handler(vlapic);
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break;
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case APIC_OFFSET_SELF_IPI:
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break;
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case APIC_OFFSET_VER:
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case APIC_OFFSET_APR:
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case APIC_OFFSET_PPR:
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@ -80,7 +80,6 @@
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#define APIC_OFFSET_TIMER_ICR 0x380U /* Timer's Initial Count */
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#define APIC_OFFSET_TIMER_CCR 0x390U /* Timer's Current Count */
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#define APIC_OFFSET_TIMER_DCR 0x3E0U /* Timer's Divide Configuration */
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#define APIC_OFFSET_SELF_IPI 0x3F0U /* Self IPI register */
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/*
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* 16 priority levels with at most one vector injected per level.
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