hv: cpuid: make leaf 0x4 per-cpu in hybrid architecture
Leaf 0x4 returns deterministic cache parameters for each level. In hybrid architecture, P-cores and E-cores have different cache information. Add leaf 0x4 to per-cpu list in hybrid architecture and handle specific cpuid access. Tracked-On: #8608 Signed-off-by: Haiwei Li <haiwei.li@intel.com>
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Haiwei Li
acrnsi-robot
parent
f7506424e4
commit
59a8cc4c28
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@ -443,6 +443,50 @@ static int32_t set_vcpuid_vcat_10h(struct acrn_vm *vm)
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}
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#endif
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static void guest_cpuid_04h(__unused struct acrn_vm *vm, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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struct vcpuid_entry entry;
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cpuid_subleaf(CPUID_CACHE, *ecx, &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
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if (entry.eax != 0U) {
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#ifdef CONFIG_VCAT_ENABLED
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if (is_vcat_configured(vm)) {
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/* set_vcpuid_vcat_04h will not change entry.eax */
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result = set_vcpuid_vcat_04h(vm, &entry);
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}
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#endif
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}
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*eax = entry.eax;
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*ebx = entry.ebx;
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*ecx = entry.ecx;
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*edx = entry.edx;
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}
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static int32_t set_vcpuid_cache(struct acrn_vm *vm)
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{
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int32_t result = 0;
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struct vcpuid_entry entry;
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uint32_t i;
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entry.leaf = CPUID_CACHE;
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entry.flags = CPUID_CHECK_SUBLEAF;
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for (i = 0U; ; i++) {
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entry.subleaf = i;
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entry.ecx = i;
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guest_cpuid_04h(vm, &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
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if (entry.eax == 0U) {
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break;
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}
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result = set_vcpuid_entry(vm, &entry);
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if (result != 0) {
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/* wants to break out of switch */
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break;
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}
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}
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return result;
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}
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static int32_t set_vcpuid_extended_function(struct acrn_vm *vm)
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{
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uint32_t i, limit;
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@ -526,6 +570,15 @@ static inline void percpu_cpuid_init(void)
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pcpu_cpuids.leaf_nr = sizeof(percpu_leaves)/sizeof(uint32_t);
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memcpy_s(pcpu_cpuids.leaves, sizeof(percpu_leaves),
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percpu_leaves, sizeof(percpu_leaves));
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/* hybrid related percpu leaves*/
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if (pcpu_has_cap(X86_FEATURE_HYBRID)) {
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/* 0x4U */
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uint32_t hybrid_leaves[] = {CPUID_CACHE};
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memcpy_s((pcpu_cpuids.leaves + pcpu_cpuids.leaf_nr * sizeof(uint32_t)),
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sizeof(hybrid_leaves), hybrid_leaves, sizeof(hybrid_leaves));
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pcpu_cpuids.leaf_nr += sizeof(hybrid_leaves)/sizeof(uint32_t);
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}
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}
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int32_t set_vcpuid_entries(struct acrn_vm *vm)
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@ -533,7 +586,7 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
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int32_t result;
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struct vcpuid_entry entry;
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uint32_t limit;
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uint32_t i, j;
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uint32_t i;
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struct cpuinfo_x86 *cpu_info = get_pcpu_info();
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init_vcpuid_entry(0U, 0U, 0U, &entry);
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@ -554,24 +607,9 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
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}
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switch (i) {
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case 0x04U:
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for (j = 0U; ; j++) {
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init_vcpuid_entry(i, j, CPUID_CHECK_SUBLEAF, &entry);
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if (entry.eax == 0U) {
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break;
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}
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#ifdef CONFIG_VCAT_ENABLED
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if (is_vcat_configured(vm)) {
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result = set_vcpuid_vcat_04h(vm, &entry);
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}
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#endif
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result = set_vcpuid_entry(vm, &entry);
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if (result != 0) {
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/* wants to break out of switch */
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break;
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}
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}
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/* 0x4U */
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case CPUID_CACHE:
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result = set_vcpuid_cache(vm);
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break;
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/* MONITOR/MWAIT */
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case 0x05U:
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@ -883,6 +921,11 @@ void guest_cpuid(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t
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guest_cpuid_01h(vcpu, eax, ebx, ecx, edx);
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break;
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/* 0x04U for hybrid arch */
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case CPUID_CACHE:
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guest_cpuid_04h(vcpu->vm, eax, ebx, ecx, edx);
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break;
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case 0x0bU:
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guest_cpuid_0bh(vcpu, eax, ebx, ecx, edx);
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break;
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@ -905,7 +948,7 @@ void guest_cpuid(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx, uint32_t
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default:
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/*
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* In this switch statement, leaf 0x01/0x0b/0x0d/0x19/0x1f/0x80000001
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* In this switch statement, leaf 0x01/0x04/0x0b/0x0d/0x19/0x1f/0x80000001
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* shall be handled specifically. All the other cases
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* just return physical value.
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*/
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@ -85,6 +85,7 @@
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/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
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#define X86_FEATURE_MDS_CLEAR ((FEAT_7_0_EDX << 5U) + 10U)
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#define X86_FEATURE_HYBRID ((FEAT_7_0_EDX << 5U) + 15U)
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#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U)
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#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5U) + 27U)
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#define X86_FEATURE_L1D_FLUSH ((FEAT_7_0_EDX << 5U) + 28U)
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@ -120,6 +120,8 @@
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#define CPUID_ECX_SGX_LC (1U<<30U)
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/* CPUID.07H:ECX.PKS*/
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#define CPUID_ECX_PKS (1U<<31U)
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/* CPUID.07H:EDX.Hybrid */
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#define CPUID_EDX_HYBRID (1U<<15U)
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/* CPUID.07H:EDX.CET_IBT */
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#define CPUID_EDX_CET_IBT (1U<<20U)
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/* CPUID.07H:EDX.IBRS_IBPB*/
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@ -166,6 +168,7 @@
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#define CPUID_FEATURES 1U
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#define CPUID_TLB 2U
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#define CPUID_SERIALNUM 3U
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#define CPUID_CACHE 4U
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#define CPUID_EXTEND_FEATURE 7U
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#define CPUID_EXTEND_TOPOLOGY 0xBU
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#define CPUID_XSAVE_FEATURES 0xDU
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