hv: mmu: rename PTT_HOST to PTT_PRIMARY

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Li, Fei1 2018-08-23 14:19:44 +08:00 committed by lijinxia
parent c102c44c16
commit 58fffcd3b9
5 changed files with 8 additions and 8 deletions

View File

@ -244,7 +244,7 @@ void init_paging(void)
/* Map all memory regions to UC attribute */ /* Map all memory regions to UC attribute */
mmu_add((uint64_t *)mmu_pml4_addr, e820_mem.mem_bottom, mmu_add((uint64_t *)mmu_pml4_addr, e820_mem.mem_bottom,
e820_mem.mem_bottom, e820_mem.mem_top - e820_mem.mem_bottom, e820_mem.mem_bottom, e820_mem.mem_top - e820_mem.mem_bottom,
attr_uc, PTT_HOST); attr_uc, PTT_PRIMARY);
/* Modify WB attribute for E820_TYPE_RAM */ /* Modify WB attribute for E820_TYPE_RAM */
for (i = 0U; i < e820_entries; i++) { for (i = 0U; i < e820_entries; i++) {
@ -253,7 +253,7 @@ void init_paging(void)
mmu_modify_or_del((uint64_t *)mmu_pml4_addr, mmu_modify_or_del((uint64_t *)mmu_pml4_addr,
entry->baseaddr, entry->length, entry->baseaddr, entry->length,
PAGE_CACHE_WB, PAGE_CACHE_MASK, PAGE_CACHE_WB, PAGE_CACHE_MASK,
PTT_HOST, MR_MODIFY); PTT_PRIMARY, MR_MODIFY);
} }
} }
@ -263,7 +263,7 @@ void init_paging(void)
hv_hpa = get_hv_image_base(); hv_hpa = get_hv_image_base();
mmu_modify_or_del((uint64_t *)mmu_pml4_addr, hv_hpa, CONFIG_RAM_SIZE, mmu_modify_or_del((uint64_t *)mmu_pml4_addr, hv_hpa, CONFIG_RAM_SIZE,
PAGE_CACHE_WB, PAGE_CACHE_MASK | PAGE_USER, PAGE_CACHE_WB, PAGE_CACHE_MASK | PAGE_USER,
PTT_HOST, MR_MODIFY); PTT_PRIMARY, MR_MODIFY);
/* Enable paging */ /* Enable paging */
enable_paging(HVA2HPA(mmu_pml4_addr)); enable_paging(HVA2HPA(mmu_pml4_addr));

View File

@ -48,7 +48,7 @@ static int split_large_page(uint64_t *pte,
paddr += paddrinc; paddr += paddrinc;
} }
ref_prot = (ptt == PTT_HOST) ? PAGE_TABLE : EPT_RWX; ref_prot = (ptt == PTT_PRIMARY) ? PAGE_TABLE : EPT_RWX;
set_pgentry(pte, HVA2HPA((void *)pbase) | ref_prot); set_pgentry(pte, HVA2HPA((void *)pbase) | ref_prot);
/* TODO: flush the TLB */ /* TODO: flush the TLB */
@ -80,7 +80,7 @@ static inline int construct_pgentry(enum _page_table_type ptt, uint64_t *pde)
return -ENOMEM; return -ENOMEM;
} }
prot = (ptt == PTT_HOST) ? PAGE_TABLE: EPT_RWX; prot = (ptt == PTT_PRIMARY) ? PAGE_TABLE: EPT_RWX;
set_pgentry(pde, HVA2HPA(pd_page) | prot); set_pgentry(pde, HVA2HPA(pd_page) | prot);
return 0; return 0;
} }

View File

@ -197,7 +197,7 @@ int general_sw_loader(struct vm *vm, struct vcpu *vcpu)
* reserving. Current strategy is "total_mem_size in Giga - * reserving. Current strategy is "total_mem_size in Giga -
* remained 1G pages" for reserving. * remained 1G pages" for reserving.
*/ */
if (is_vm0(vm) && check_mmu_1gb_support(PTT_HOST)) { if (is_vm0(vm) && check_mmu_1gb_support(PTT_PRIMARY)) {
int32_t reserving_1g_pages; int32_t reserving_1g_pages;
#ifdef CONFIG_REMAIN_1G_PAGES #ifdef CONFIG_REMAIN_1G_PAGES

View File

@ -215,7 +215,7 @@
#define ROUND_PAGE_DOWN(addr) ((addr) & CPU_PAGE_MASK) #define ROUND_PAGE_DOWN(addr) ((addr) & CPU_PAGE_MASK)
enum _page_table_type { enum _page_table_type {
PTT_HOST = 0, /* Mapping for hypervisor */ PTT_PRIMARY = 0, /* Mapping for hypervisor */
PTT_EPT = 1, PTT_EPT = 1,
PAGETABLE_TYPE_UNKNOWN, PAGETABLE_TYPE_UNKNOWN,
}; };

View File

@ -96,7 +96,7 @@ static inline uint64_t pdpte_large(uint64_t pdpte)
static inline uint64_t pgentry_present(enum _page_table_type ptt, uint64_t pte) static inline uint64_t pgentry_present(enum _page_table_type ptt, uint64_t pte)
{ {
return (ptt == PTT_HOST) ? (pte & PAGE_PRESENT) : (pte & EPT_RWX); return (ptt == PTT_PRIMARY) ? (pte & PAGE_PRESENT) : (pte & EPT_RWX);
} }
#endif /* PGTABLE_H */ #endif /* PGTABLE_H */