fix "negative shift"
MISRA C doesn't allowed negative shift, changed any potential signed value to unsigned value. Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -59,7 +59,7 @@ int ibrs_type;
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inline bool cpu_has_cap(uint32_t bit)
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{
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int feat_idx = bit >> 5;
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int feat_bit = bit & 0x1fU;
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uint32_t feat_bit = bit & 0x1fU;
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if (feat_idx >= FEATURE_WORDS)
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return false;
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@ -127,7 +127,8 @@ enum vm_paging_mode get_vcpu_paging_mode(struct vcpu *vcpu)
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static int _gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_info,
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uint64_t gva, uint64_t *gpa, uint32_t *err_code)
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{
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int i, index, shift;
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int i, index;
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uint32_t shift;
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uint8_t *base;
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uint64_t entry;
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uint64_t addr, page_size;
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@ -1407,7 +1407,8 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
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void *memarg)
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{
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uint64_t val, rflags;
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int error, bitmask, bitoff;
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int error, bitmask;
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uint32_t bitoff;
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/*
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* 0F BA is a Group 8 extended opcode.
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@ -223,8 +223,8 @@ vioapic_update_tmr(struct vcpu *vcpu)
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static uint32_t
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vioapic_read(struct vioapic *vioapic, uint32_t addr)
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{
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uint32_t regnum;
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int pin, rshift;
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uint32_t regnum, rshift;
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int pin;
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regnum = addr & 0xffU;
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switch (regnum) {
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@ -291,8 +291,8 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
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{
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uint64_t data64, mask64;
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uint64_t last, new, changed;
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uint32_t regnum;
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int pin, lshift;
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uint32_t regnum, lshift;
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int pin;
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regnum = addr & 0xffUL;
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switch (regnum) {
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@ -712,8 +712,9 @@ vlapic_update_ppr(struct vlapic *vlapic)
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/* update ppr */
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{
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int i, lastprio, curprio, vector, idx;
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int i, lastprio, curprio, idx;
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struct lapic_reg *isrptr;
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uint32_t vector;
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if (vlapic->isrvec_stk_top == 0 && isrvec != 0)
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panic("isrvec_stk is corrupted: %d", isrvec);
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@ -738,9 +739,9 @@ vlapic_update_ppr(struct vlapic *vlapic)
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*/
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i = 1;
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isrptr = &vlapic->apic_page->isr[0];
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for (vector = 0; vector < 256; vector++) {
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idx = vector / 32;
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if ((isrptr[idx].val & (1U << (vector % 32))) != 0U) {
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for (vector = 0U; vector < 256U; vector++) {
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idx = vector / 32U;
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if ((isrptr[idx].val & (1U << (vector % 32U))) != 0U) {
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if ((i > vlapic->isrvec_stk_top) ||
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((i < ISRVEC_STK_SIZE) &&
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(vlapic->isrvec_stk[i] != vector))) {
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@ -191,7 +191,7 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
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rte.lo_32 |= IOAPIC_RTE_INTALO;
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/* Dest field */
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rte.hi_32 |= ALL_CPUS_MASK << 24;
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rte.hi_32 |= ALL_CPUS_MASK << 24U;
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return rte;
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}
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@ -66,7 +66,7 @@
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#define iommu_cap_plmr(c) (((c) >> 5) & 1UL)
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#define iommu_cap_rwbf(c) (((c) >> 4) & 1UL)
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#define iommu_cap_afl(c) (((c) >> 3) & 1UL)
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#define iommu_cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7UL)))
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#define iommu_cap_ndoms(c) ((1U) << (4U + 2U * ((c) & 0x7U)))
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/*
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* Decoding Extended Capability Register
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