From 4ef991effb99a9d9026f16a307cc8a291c0e01e6 Mon Sep 17 00:00:00 2001
From: "David B. Kinder" <david.b.kinder@intel.com>
Date: Thu, 11 Aug 2022 17:46:21 -0700
Subject: [PATCH] doc: add MCE check avoidance explanation

Add a reference to the intel.com white paper on MCE avoidance to the
Disable MCE Workaround configuration option

Tracked-On: #7978

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
---
 misc/config_tools/schema/config.xsd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/misc/config_tools/schema/config.xsd b/misc/config_tools/schema/config.xsd
index 1208f0da5..62cd2d740 100644
--- a/misc/config_tools/schema/config.xsd
+++ b/misc/config_tools/schema/config.xsd
@@ -111,7 +111,7 @@ If your VM is not a security VM, leave this option unchecked. </xs:documentation
     </xs:element>
     <xs:element name="MCE_ON_PSC_DISABLED" type="Boolean" default="n">
       <xs:annotation acrn:title="Disable MCE workaround" acrn:views="advanced">
-        <xs:documentation>Disable the software workaround for Machine Check Error on Page Size Change (erratum in some processor families).</xs:documentation>
+        <xs:documentation>Disable the software workaround for Machine Check Error on Page Size Change (erratum in some processor families).  For more information about this workaround and affected processors, see this `MCE Avoidance on Page Size Change White Paper &lt;https://www.intel.com/content/www/us/en/developer/articles/troubleshooting/software-security-guidance/technical-documentation/machine-check-error-avoidance-page-size-change.html&gt;`_.</xs:documentation>
       </xs:annotation>
     </xs:element>
     <xs:element name="RDT" type="RDTType">