HV:treewide: Clean up -1U or -1UL
According to C99 standard, -1 integer constant with 'U/UL' suffix has no type. To explicit the integer constant: Update -1U or -1UL as ~0U or ~0UL, or invalid number according to usage case. V1-->V2: Update parameter name and type of send_startup_ipi since the second parameter is used as pcpu_id; Update related comments for code clearity. V2-->V3: Update comments of struct acrn_irqline; rename cpu_startup_dest as dest_pcpu_id in the second parameter of send_startup_ipi. Tracked-on: ccm0001001-247033 Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -206,7 +206,7 @@ struct acrn_irqline {
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uint64_t pic_irq;
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/** ioapic IRQ for IOAPIC & ISA TYPE,
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* if -1 then this IRQ will not be injected
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* if ~0UL then this IRQ will not be injected
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*/
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uint64_t ioapic_irq;
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} __aligned(8);
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@ -713,9 +713,12 @@ void start_cpus()
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*/
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expected_up = phys_cpu_num;
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/* Broadcast IPIs to all other CPUs */
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/* Broadcast IPIs to all other CPUs,
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* In this case, INTR_CPU_STARTUP_ALL_EX_SELF decides broadcasting
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* IPIs, INVALID_CPU_ID is parameter value to destination pcpu_id.
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*/
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send_startup_ipi(INTR_CPU_STARTUP_ALL_EX_SELF,
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-1U, startup_paddr);
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INVALID_CPU_ID, startup_paddr);
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/* Wait until global count is equal to expected CPU up count or
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* configured time-out has expired
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@ -483,7 +483,7 @@ vlapic_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level)
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static inline int
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lvt_off_to_idx(uint32_t offset)
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{
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uint32_t index = -1U;
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uint32_t index = ~0U;
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switch (offset) {
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case APIC_OFFSET_CMCI_LVT:
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@ -352,7 +352,7 @@ uint8_t get_cur_lapic_id(void)
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int
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send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
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uint32_t cpu_startup_dest, uint64_t cpu_startup_start_address)
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uint16_t dest_pcpu_id, uint64_t cpu_startup_start_address)
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{
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union apic_icr icr;
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uint8_t shorthand;
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@ -368,7 +368,7 @@ send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
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if (cpu_startup_shorthand == INTR_CPU_STARTUP_USE_DEST) {
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shorthand = INTR_LAPIC_ICR_USE_DEST_ARRAY;
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icr.x_bits.dest_field = per_cpu(lapic_id, cpu_startup_dest);
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icr.x_bits.dest_field = per_cpu(lapic_id, dest_pcpu_id);
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} else { /* Use destination shorthand */
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shorthand = INTR_LAPIC_ICR_ALL_EX_SELF;
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icr.value_32.hi_32 = 0;
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@ -1280,10 +1280,10 @@ static void init_exec_ctrl(struct vcpu *vcpu)
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* that support the 1-setting of the "virtual-interrupt
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* delivery" VM-execution control
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*/
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exec_vmwrite64(VMX_EOI_EXIT0_FULL, -1UL);
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exec_vmwrite64(VMX_EOI_EXIT1_FULL, -1UL);
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exec_vmwrite64(VMX_EOI_EXIT2_FULL, -1UL);
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exec_vmwrite64(VMX_EOI_EXIT3_FULL, -1UL);
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exec_vmwrite64(VMX_EOI_EXIT0_FULL, ~0UL);
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exec_vmwrite64(VMX_EOI_EXIT1_FULL, ~0UL);
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exec_vmwrite64(VMX_EOI_EXIT2_FULL, ~0UL);
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exec_vmwrite64(VMX_EOI_EXIT3_FULL, ~0UL);
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}
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}
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@ -105,8 +105,8 @@ static int handle_virt_irqline(struct vm *vm, uint64_t target_vmid,
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/* Call vpic for pic injection */
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ret = handle_vpic_irqline(target_vm, param->pic_irq, mode);
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/* call vioapic for ioapic injection if ioapic_irq != -1*/
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if (param->ioapic_irq != -1UL) {
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/* call vioapic for ioapic injection if ioapic_irq != ~0UL*/
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if (param->ioapic_irq != (~0UL)) {
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/* handle IOAPIC irqline */
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ret = handle_vioapic_irqline(target_vm,
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param->ioapic_irq, mode);
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@ -144,7 +144,7 @@ int init_lapic(uint16_t cpu_id);
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void send_lapic_eoi(void);
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uint8_t get_cur_lapic_id(void);
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int send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
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uint32_t cpu_startup_dest,
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uint16_t dest_pcpu_id,
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uint64_t cpu_startup_start_address);
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/* API to send an IPI to a single guest */
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void send_single_ipi(uint16_t pcpu_id, uint32_t vector);
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@ -186,7 +186,7 @@ struct acrn_irqline {
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uint64_t pic_irq;
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/** ioapic IRQ for IOAPIC & ISA TYPE,
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* if -1 then this IRQ will not be injected
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* if ~0UL then this IRQ will not be injected
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*/
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uint64_t ioapic_irq;
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} __aligned(8);
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@ -77,7 +77,7 @@
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#define ACRN_DOM0_VMID (0UL)
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#define ACRN_INVALID_VMID (-1)
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#define ACRN_INVALID_HPA (-1UL)
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#define ACRN_INVALID_HPA (~0UL)
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/* Generic memory attributes */
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#define MEM_ACCESS_READ 0x00000001U
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