HV: reimplement PCI device discovery
Major changes: 1. Correct handling of device multi-function capability We only check function zero for this feature. If it has it, we continue looking at all remaining functions, ignoring those with invalid vendors. The PCI spec says we are not to probe beyond function zero if it does not exist or indicates it is not a multi-function device. 2a. Walk *ALL* buses in the PCI space, however, Before walking the PCI hierarchy, post-processed ACPI DMAR info is parsed and a map is created between all device-scopes across all DRHDs and the corresponding IOMMU index. This map is used at the time of walking the PCI hierarchy. If a BDF that ACRN is currently working on, is found in the above-mentioned map, the BDF device is mapped to the corresponding DRHD in the map. If the BDF were a bridge type, realized with "Header Type" in config space, the BDF device along with all its downstream devices are mapped to the corresponding DRHD in the map. To avoid walking previously visited buses, we maintain a bitmap that stores which bus is walked when we handle Bridge type devices. Once ACPI information is included into ACRN about the PCI-Express Root Complexes / PCI Host Bridges, we can avoid the final loop which probes all remainder buses, and instead jump to the next Host Bridge bus. From prior patches, init_pdev returns the pdev structure it created to the caller. This allows us to complete initialization by updating its drhd_idx to the correct DRHD. Tracked-On: #4134 Signed-off-by: Alexander Merritt <alex.merritt@intel.com> Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Sainath Grandhi
wenlingz
parent
94a456ae24
commit
422330d4ab
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@ -38,16 +38,19 @@
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#include <uart16550.h>
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#include <logmsg.h>
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#include <pci_dev.h>
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#include <vtd.h>
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#include <bits.h>
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#include <board.h>
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static spinlock_t pci_device_lock;
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static uint32_t num_pci_pdev;
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static struct pci_pdev pci_pdev_array[CONFIG_MAX_PCI_DEV_NUM];
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static void init_pdev(uint16_t pbdf);
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static void init_pdev(uint16_t pbdf, uint32_t drhd_index);
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/* @brief: Find the DRHD index corresponding to a PCI device
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* Runs through the pci_pdev_array and returns the value in drhd_idx
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* member from pdev strucutre that matches matches B:D.F
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* member from pdev structure that matches matches B:D.F
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*
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* @pbdf[in] B:D.F of a PCI device
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*
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@ -151,69 +154,225 @@ void enable_disable_pci_intx(union pci_bdf bdf, bool enable)
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}
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}
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#define BUS_SCAN_SKIP 0U
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#define BUS_SCAN_PENDING 1U
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#define BUS_SCAN_COMPLETE 2U
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void init_pci_pdev_list(void)
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static bool is_hidden_pdev(union pci_bdf pbdf)
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{
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bool hidden = false;
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/* if it is debug uart, hide it*/
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if (is_pci_dbg_uart(pbdf)) {
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pr_info("hide pci uart dev: (%x:%x:%x)", pbdf.bits.b, pbdf.bits.d, pbdf.bits.f);
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hidden = true;
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}
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return hidden;
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}
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static void pci_init_pdev(union pci_bdf pbdf, uint32_t drhd_index)
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{
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if (!is_hidden_pdev(pbdf)) {
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init_pdev(pbdf.value, drhd_index);
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}
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}
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/*
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* quantity of uint64_t to encode a bitmap of all bus values
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* TODO: PCI_BUSMAX is a good candidate to move to
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* generated platform files.
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*/
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#define BUSES_BITMAP_LEN ((PCI_BUSMAX + 1U) >> 6U)
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/*
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* must be >= total Endpoints in all DRDH devscope
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* TODO: BDF_SET_LEN is a good candidate to move to
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* generated platform files.
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*/
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#define BDF_SET_LEN 32U
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struct pci_bdf_to_iommu {
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union pci_bdf dev_scope_bdf;
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uint32_t dev_scope_drhd_index;
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};
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struct pci_bdf_set {
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uint32_t pci_bdf_map_count;
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struct pci_bdf_to_iommu bdf_map[BDF_SET_LEN];
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};
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struct pci_bus_set {
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uint8_t bus_under_scan;
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uint32_t bus_drhd_index;
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};
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static uint32_t pci_check_override_drhd_index(union pci_bdf pbdf,
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const struct pci_bdf_set *const bdfs_from_drhds,
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uint32_t current_drhd_index)
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{
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uint16_t bdfi;
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uint32_t bdf_drhd_index = current_drhd_index;
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for (bdfi = 0U; bdfi < bdfs_from_drhds->pci_bdf_map_count; bdfi++) {
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if (bdfs_from_drhds->bdf_map[bdfi].dev_scope_bdf.value == pbdf.value) {
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/*
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* Override current_drhd_index
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*/
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bdf_drhd_index =
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bdfs_from_drhds->bdf_map[bdfi].dev_scope_drhd_index;
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}
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}
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return bdf_drhd_index;
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}
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/* Scan part of PCI hierarchy, starting with the given bus. */
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static void init_pci_hierarchy(uint8_t bus, uint64_t buses_visited[BUSES_BITMAP_LEN],
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const struct pci_bdf_set *const bdfs_from_drhds, uint32_t drhd_index)
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{
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bool is_mfdev;
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uint32_t vendor;
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uint8_t hdr_type, dev, func;
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union pci_bdf pbdf;
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uint8_t hdr_type, secondary_bus, dev, func;
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uint32_t bus, val;
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uint8_t bus_to_scan[PCI_BUSMAX + 1] = { BUS_SCAN_SKIP };
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uint8_t current_bus_index;
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uint32_t current_drhd_index, bdf_drhd_index;
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/* start from bus 0 */
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bus_to_scan[0U] = BUS_SCAN_PENDING;
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struct pci_bus_set bus_map[PCI_BUSMAX + 1U]; /* FIFO queue of buses to walk */
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uint32_t s = 0U, e = 0U; /* start and end index into queue */
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for (bus = 0U; bus <= PCI_BUSMAX; bus++) {
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if (bus_to_scan[bus] != BUS_SCAN_PENDING) {
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continue;
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}
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bus_map[e].bus_under_scan = bus;
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bus_map[e].bus_drhd_index = drhd_index;
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e = e + 1U;
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while (s < e) {
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current_bus_index = bus_map[s].bus_under_scan;
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current_drhd_index = bus_map[s].bus_drhd_index;
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s = s + 1U;
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bus_to_scan[bus] = BUS_SCAN_COMPLETE;
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pbdf.bits.b = (uint8_t)bus;
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bitmap_set_nolock(current_bus_index,
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&buses_visited[current_bus_index >> 6U]);
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pbdf.bits.b = current_bus_index;
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for (dev = 0U; dev <= PCI_SLOTMAX; dev++) {
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pbdf.bits.d = dev;
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is_mfdev = false;
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for (func = 0U; func <= PCI_FUNCMAX; func++) {
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pbdf.bits.f = func;
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val = pci_pdev_read_cfg(pbdf, PCIR_VENDOR, 4U);
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if ((val == 0xFFFFFFFFU) || (val == 0U) || (val == 0xFFFF0000U) || (val == 0xFFFFU)) {
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/* If function 0 is not implemented, skip to next device */
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if (func == 0U) {
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break;
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}
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vendor = read_pci_pdev_cfg_vendor(pbdf);
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hdr_type = read_pci_pdev_cfg_headertype(pbdf);
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/* continue scan next function */
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if (func == 0U) {
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is_mfdev = is_pci_cfg_multifunction(hdr_type);
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}
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/* Do not probe beyond function 0 if not a multi-function device
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* TODO unless device supports ARI or SR-IOV
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* (PCIe spec r5.0 §7.5.1.1.9)
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*/
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if (((func == 0U) && !is_pci_vendor_valid(vendor)) ||
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((func > 0U) && (!is_mfdev))) {
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break;
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}
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if (!is_pci_vendor_valid(vendor)) {
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continue;
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}
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/* if it is debug uart, hide it from SOS */
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if (is_pci_dbg_uart(pbdf)) {
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pr_info("hide pci uart dev: (%x:%x:%x)", pbdf.bits.b, pbdf.bits.d, pbdf.bits.f);
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continue;
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}
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bdf_drhd_index = pci_check_override_drhd_index(pbdf, bdfs_from_drhds,
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current_drhd_index);
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pci_init_pdev(pbdf, bdf_drhd_index);
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init_pdev(pbdf.value);
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hdr_type = (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_HDRTYPE, 1U);
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if ((hdr_type & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
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/* Secondary bus to be scanned */
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secondary_bus = (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_SECBUS_1, 1U);
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if (bus_to_scan[secondary_bus] != BUS_SCAN_SKIP) {
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pr_err("%s, bus %d may be downstream of different PCI bridges",
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__func__, secondary_bus);
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} else {
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bus_to_scan[secondary_bus] = BUS_SCAN_PENDING;
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}
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if (is_pci_cfg_bridge(hdr_type)) {
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bus_map[e].bus_under_scan = read_pci_pdev_cfg_secbus(pbdf);
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bus_map[e].bus_drhd_index = bdf_drhd_index;
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e = e + 1U;
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}
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}
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}
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}
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}
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/*
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* @brief: Setup bdfs_from_drhds data structure as the DMAR tables are walked searching
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* for PCI device scopes. bdfs_from_drhds is used later in init_pci_hierarchy
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* to map the right DRHD unit to the PCI device
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*/
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static void pci_add_bdf_from_drhd(union pci_bdf bdf, struct pci_bdf_set *const bdfs_from_drhds,
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uint32_t drhd_index)
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{
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if (bdfs_from_drhds->pci_bdf_map_count < BDF_SET_LEN) {
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bdfs_from_drhds->bdf_map[bdfs_from_drhds->pci_bdf_map_count].dev_scope_bdf = bdf;
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bdfs_from_drhds->bdf_map[bdfs_from_drhds->pci_bdf_map_count].dev_scope_drhd_index = drhd_index;
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bdfs_from_drhds->pci_bdf_map_count++;
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} else {
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ASSERT(bdfs_from_drhds->pci_bdf_map_count < BDF_SET_LEN,
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"Compare value in BDF_SET_LEN against those in ACPI DMAR tables");
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}
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}
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/*
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* @brief: Setup bdfs_from_drhds data structure as the DMAR tables are walked searching
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* for PCI device scopes. bdfs_from_drhds is used later in init_pci_hierarchy
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* to map the right DRHD unit to the PCI device.
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* TODO: bdfs_from_drhds is a good candidate to be part of generated platform
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* info.
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*/
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static void pci_parse_iommu_devscopes(struct pci_bdf_set *const bdfs_from_drhds,
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uint32_t *drhd_idx_pci_all)
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{
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union pci_bdf bdf;
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uint32_t drhd_index, devscope_index;
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for (drhd_index = 0U; drhd_index < plat_dmar_info.drhd_count; drhd_index++) {
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for (devscope_index = 0U; devscope_index < plat_dmar_info.drhd_units[drhd_index].dev_cnt;
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devscope_index++) {
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bdf.fields.bus = plat_dmar_info.drhd_units[drhd_index].devices[devscope_index].bus;
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bdf.fields.devfun = plat_dmar_info.drhd_units[drhd_index].devices[devscope_index].devfun;
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if ((plat_dmar_info.drhd_units[drhd_index].devices[devscope_index].type ==
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ACPI_DMAR_SCOPE_TYPE_ENDPOINT) ||
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(plat_dmar_info.drhd_units[drhd_index].devices[devscope_index].type ==
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ACPI_DMAR_SCOPE_TYPE_BRIDGE)) {
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pci_add_bdf_from_drhd(bdf, bdfs_from_drhds, drhd_index);
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} else {
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/*
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* Do nothing for IOAPIC, ACPI namespace and
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* MSI Capable HPET device scope
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*/
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}
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}
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}
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if ((plat_dmar_info.drhd_units[plat_dmar_info.drhd_count - 1U].flags & DRHD_FLAG_INCLUDE_PCI_ALL_MASK)
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== DRHD_FLAG_INCLUDE_PCI_ALL_MASK) {
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*drhd_idx_pci_all = plat_dmar_info.drhd_count - 1U;
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}
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}
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/*
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* @brief Walks the PCI heirarchy and initializes array of pci_pdev structs
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* Uses DRHD info from ACPI DMAR tables to cover the endpoints and
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* bridges along with their hierarchy captured in the device scope entries
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* Walks through rest of the devices starting at bus 0 and thru PCI_BUSMAX
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*/
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void init_pci_pdev_list(void)
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{
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uint64_t buses_visited[BUSES_BITMAP_LEN] = {0UL};
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struct pci_bdf_set bdfs_from_drhds;
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uint32_t drhd_idx_pci_all = INVALID_DRHD_INDEX;
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uint16_t bus;
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bool was_visited = false;
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pci_parse_iommu_devscopes(&bdfs_from_drhds, &drhd_idx_pci_all);
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/* TODO: iterate over list of PCI Host Bridges found in ACPI namespace */
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for (bus = 0U; bus <= PCI_BUSMAX; bus++) {
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was_visited = bitmap_test((bus & 0x3FU), &buses_visited[bus >> 6U]);
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if (!was_visited) {
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init_pci_hierarchy((uint8_t)bus, buses_visited, &bdfs_from_drhds, drhd_idx_pci_all);
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}
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}
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}
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static inline uint32_t pci_pdev_get_nr_bars(uint8_t hdr_type)
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{
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uint32_t nr_bars = 0U;
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@ -283,7 +442,7 @@ static void pci_read_cap(struct pci_pdev *pdev)
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}
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}
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static void init_pdev(uint16_t pbdf)
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static void init_pdev(uint16_t pbdf, uint32_t drhd_index)
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{
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uint8_t hdr_type;
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union pci_bdf bdf;
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@ -303,6 +462,8 @@ static void init_pdev(uint16_t pbdf)
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pci_read_cap(pdev);
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}
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pdev->drhd_index = drhd_index;
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fill_pci_dev_config(pdev);
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num_pci_pdev++;
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@ -237,6 +237,12 @@ uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
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void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable);
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/*
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* @brief Walks the PCI heirarchy and initializes array of pci_pdev structs
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* Uses DRHD info from ACPI DMAR tables to cover the endpoints and
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* bridges along with their hierarchy captured in the device scope entries
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* Walks through rest of the devices starting at bus 0 and thru PCI_BUSMAX
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*/
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void init_pci_pdev_list(void);
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/* @brief: Find the DRHD index corresponding to a PCI device
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