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acrn-hypervisor
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HV: Add vuart port base address/IRQ Kconfig options 

Adding Kconfig option to define the vuart port base address/IRQ.
By default, use 0x3F8/IRQ4. For MRB, use 0x3E8/IRQ6.
We are experiencing problems on NUC after changing from 0x3F8/IRQ4
to 0x3E8/IRQ6.

Tracked-On: #1817
Change-Id: Ie407e51a7bc25ac0bb4c61453c969f1466fa33ca
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen 2018-11-15 11:14:41 -08:00 committed by lijinxia
parent b32e689a64
commit 3b87e7c67f
4 changed files with 25 additions and 10 deletions
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14
hypervisor/arch/x86/Kconfig
View File

@ -165,6 +165,20 @@ config SERIAL_PIO_BASE
The base address of the UART ports. This is logically 16-bit but used
as a 64-bit integer.
config COM_BASE
hex "Base address of the vuart port"
depends on !RELEASE
default 0x3f8
help
Base address of the vuart port.
config COM_IRQ
hex "IRQ of the vuart port"
depends on !RELEASE
default 4
help
IRQ of the vuart port.
config MALLOC_ALIGN
int "Block size in the heap for malloc()"
range 8 32

6
hypervisor/arch/x86/assign.c
View File

@ -43,15 +43,17 @@ is_entry_active(const struct ptdev_remapping_info *entry)
return atomic_load32(&entry->active) == ACTIVE_FLAG;
}
#ifdef HV_DEBUG
static bool ptdev_hv_owned_intx(const struct acrn_vm *vm, const union source_id *virt_sid)
{
/* vm0 vuart pin is owned by hypervisor under debug version */
if (is_vm0(vm) && (virt_sid->intx_id.pin == COM1_IRQ)) {
if (is_vm0(vm) && (virt_sid->intx_id.pin == CONFIG_COM_IRQ)) {
return true;
} else {
return false;
}
}
#endif
static uint64_t calculate_logical_dest_mask(uint64_t pdmask)
{
@ -637,9 +639,11 @@ int ptdev_intx_pin_remap(struct acrn_vm *vm, uint8_t virt_pin,
*/
/* no remap for hypervisor owned intx */
#ifdef HV_DEBUG
if (ptdev_hv_owned_intx(vm, &virt_sid)) {
goto END;
}
#endif
/* query if we have virt to phys mapping */
spinlock_obtain(&ptdev_lock);

13
hypervisor/debug/vuart.c
View File

@ -32,7 +32,6 @@
#include "uart16550.h"
#define COM1_BASE 0x3E8U
#ifndef CONFIG_PARTITION_MODE
static char vuart_rx_buf[RX_BUF_SIZE];
@ -132,10 +131,10 @@ static void vuart_toggle_intr(const struct acrn_vuart *vu)
uint32_t operation;
intr_reason = vuart_intr_reason(vu);
vioapic_get_rte(vu->vm, COM1_IRQ, &rte);
vioapic_get_rte(vu->vm, CONFIG_COM_IRQ, &rte);
/* TODO:
* Here should assert vuart irq according to COM1_IRQ polarity.
* Here should assert vuart irq according to CONFIG_COM_IRQ polarity.
* The best way is to get the polarity info from ACIP table.
* Here we just get the info from vioapic configuration.
* based on this, we can still have irq storm during guest
@ -150,8 +149,8 @@ static void vuart_toggle_intr(const struct acrn_vuart *vu)
GSI_SET_HIGH : GSI_SET_LOW;
}
vpic_set_irq(vu->vm, COM1_IRQ, operation);
vioapic_set_irq(vu->vm, COM1_IRQ, operation);
vpic_set_irq(vu->vm, CONFIG_COM_IRQ, operation);
vioapic_set_irq(vu->vm, CONFIG_COM_IRQ, operation);
}
static void vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
@ -323,7 +322,7 @@ static void vuart_register_io_handler(struct acrn_vm *vm)
{
struct vm_io_range range = {
.flags = IO_ATTR_RW,
.base = COM1_BASE,
.base = CONFIG_COM_BASE,
.len = 8U
};
@ -402,7 +401,7 @@ void vuart_init(struct acrn_vm *vm)
vm->vuart.dlh = (uint8_t)(divisor >> 8U);
vm->vuart.active = false;
vm->vuart.base = COM1_BASE;
vm->vuart.base = CONFIG_COM_BASE;
vm->vuart.vm = vm;
vuart_fifo_init(vu);
vuart_lock_init(vu);

2
hypervisor/include/debug/vuart.h
View File

@ -69,13 +69,11 @@ struct acrn_vuart {
extern int8_t vuart_vmid;
#endif
#ifdef HV_DEBUG
#define COM1_IRQ 6U
void vuart_init(struct acrn_vm *vm);
struct acrn_vuart *vuart_console_active(void);
void vuart_console_tx_chars(struct acrn_vuart *vu);
void vuart_console_rx_chars(struct acrn_vuart *vu);
#else
#define COM1_IRQ 0xFFU
static inline void vuart_init(__unused struct acrn_vm *vm)
{
}