hv: vCAT: initialize the emulated_guest_msrs array for CAT msrs during platform initialization
Initialize the emulated_guest_msrs[] array at runtime for MSR_IA32_type_MASK_n and MSR_IA32_PQR_ASSOC msrs, there is no good way to do this initialization statically at build time Tracked-On: #5917 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -186,6 +186,10 @@ void init_pcpu_pre(bool is_bsp)
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panic("System IOAPIC info is incorrect!");
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}
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#ifdef CONFIG_VCAT_ENABLED
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init_intercepted_cat_msr_list();
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#endif
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#ifdef CONFIG_RDT_ENABLED
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init_rdt_info();
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#endif
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@ -28,7 +28,7 @@
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#define INTERCEPT_WRITE (1U << 1U)
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#define INTERCEPT_READ_WRITE (INTERCEPT_READ | INTERCEPT_WRITE)
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static const uint32_t emulated_guest_msrs[NUM_GUEST_MSRS] = {
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static uint32_t emulated_guest_msrs[NUM_GUEST_MSRS] = {
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/*
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* MSRs that trusty may touch and need isolation between secure and normal world
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* This may include MSR_IA32_STAR, MSR_IA32_LSTAR, MSR_IA32_FMASK,
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@ -79,6 +79,24 @@ static const uint32_t emulated_guest_msrs[NUM_GUEST_MSRS] = {
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#ifdef CONFIG_NVMX_ENABLED
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LIST_OF_VMX_MSRS,
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#endif
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/* The following range of elements are reserved for vCAT usage and are
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* initialized dynamically by init_intercepted_cat_msr_list() during platform initialization:
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* [(NUM_GUEST_MSRS - NUM_VCAT_MSRS) ... (NUM_GUEST_MSRS - 1)] = {
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* The following layout of each CAT MSR entry is determined by cat_msr_to_index_of_emulated_msr():
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* MSR_IA32_L3_MASK_BASE,
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* MSR_IA32_L3_MASK_BASE + 1,
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* ...
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* MSR_IA32_L3_MASK_BASE + NUM_VCAT_L3_MSRS - 1,
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*
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* MSR_IA32_L2_MASK_BASE + NUM_VCAT_L3_MSRS,
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* MSR_IA32_L2_MASK_BASE + NUM_VCAT_L3_MSRS + 1,
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* ...
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* MSR_IA32_L2_MASK_BASE + NUM_VCAT_L3_MSRS + NUM_VCAT_L2_MSRS - 1,
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*
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* MSR_IA32_PQR_ASSOC + NUM_VCAT_L3_MSRS + NUM_VCAT_L2_MSRS
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* }
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*/
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};
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static const uint32_t mtrr_msrs[] = {
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@ -355,6 +373,74 @@ void init_emulated_msrs(struct acrn_vcpu *vcpu)
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vcpu_set_guest_msr(vcpu, MSR_IA32_FEATURE_CONTROL, val64);
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}
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#ifdef CONFIG_VCAT_ENABLED
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/**
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* @brief Map CAT MSR address to zero based index
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*
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* @pre ((msr >= MSR_IA32_L3_MASK_BASE) && msr < (MSR_IA32_L3_MASK_BASE + NUM_VCAT_L3_MSRS))
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* || ((msr >= MSR_IA32_L2_MASK_BASE) && msr < (MSR_IA32_L2_MASK_BASE + NUM_VCAT_L2_MSRS))
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* || (msr == MSR_IA32_PQR_ASSOC)
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*/
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static uint32_t cat_msr_to_index_of_emulated_msr(uint32_t msr)
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{
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uint32_t index = 0U;
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/* L3 MSRs indices assignment for MSR_IA32_L3_MASK_BASE ~ (MSR_IA32_L3_MASK_BASE + NUM_VCAT_L3_MSRS):
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* 0
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* 1
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* ...
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* (NUM_VCAT_L3_MSRS - 1)
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*
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* L2 MSRs indices assignment:
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* NUM_VCAT_L3_MSRS
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* ...
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* NUM_VCAT_L3_MSRS + NUM_VCAT_L2_MSRS - 1
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* PQR index assignment for MSR_IA32_PQR_ASSOC:
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* NUM_VCAT_L3_MSRS
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*/
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if ((msr >= MSR_IA32_L3_MASK_BASE) && (msr < (MSR_IA32_L3_MASK_BASE + NUM_VCAT_L3_MSRS))) {
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index = msr - MSR_IA32_L3_MASK_BASE;
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} else if ((msr >= MSR_IA32_L2_MASK_BASE) && (msr < (MSR_IA32_L2_MASK_BASE + NUM_VCAT_L2_MSRS))) {
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index = msr - MSR_IA32_L2_MASK_BASE + NUM_VCAT_L3_MSRS;
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} else if (msr == MSR_IA32_PQR_ASSOC) {
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index = NUM_VCAT_L3_MSRS + NUM_VCAT_L2_MSRS;
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} else {
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ASSERT(false, "invalid CAT msr address");
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}
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return index;
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}
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static void init_cat_msr_entry(uint32_t msr)
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{
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/* Get index into the emulated_guest_msrs[] table for a given CAT MSR */
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uint32_t index = cat_msr_to_index_of_emulated_msr(msr) + CAT_MSR_START_INDEX;
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emulated_guest_msrs[index] = msr;
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}
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/* Init emulated_guest_msrs[] dynamically for CAT MSRs */
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void init_intercepted_cat_msr_list(void)
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{
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uint32_t msr;
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/* MSR_IA32_L2_MASK_n MSRs */
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for (msr = MSR_IA32_L2_MASK_BASE; msr < (MSR_IA32_L2_MASK_BASE + NUM_VCAT_L2_MSRS); msr++) {
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init_cat_msr_entry(msr);
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}
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/* MSR_IA32_L3_MASK_n MSRs */
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for (msr = MSR_IA32_L3_MASK_BASE; msr < (MSR_IA32_L3_MASK_BASE + NUM_VCAT_L3_MSRS); msr++) {
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init_cat_msr_entry(msr);
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}
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/* MSR_IA32_PQR_ASSOC */
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init_cat_msr_entry(MSR_IA32_PQR_ASSOC);
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}
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#endif
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/**
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* @pre vcpu != NULL
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*/
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@ -29,6 +29,7 @@
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#include <asm/guest/instr_emul.h>
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#include <asm/guest/nested.h>
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#include <asm/vmx.h>
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#include <asm/vm_config.h>
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/**
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* @brief vcpu
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@ -173,11 +174,29 @@ enum reset_mode;
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#define NUM_WORLD_MSRS 2U
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#define NUM_COMMON_MSRS 23U
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#ifdef CONFIG_VCAT_ENABLED
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#define NUM_VCAT_L2_MSRS MAX_CACHE_CLOS_NUM_ENTRIES
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#define NUM_VCAT_L3_MSRS MAX_CACHE_CLOS_NUM_ENTRIES
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/* L2/L3 mask MSRs plus MSR_IA32_PQR_ASSOC */
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#define NUM_VCAT_MSRS (NUM_VCAT_L2_MSRS + NUM_VCAT_L3_MSRS + 1U)
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#ifdef CONFIG_NVMX_ENABLED
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#define NUM_GUEST_MSRS (NUM_WORLD_MSRS + NUM_COMMON_MSRS + NUM_VMX_MSRS)
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#define CAT_MSR_START_INDEX (NUM_WORLD_MSRS + NUM_COMMON_MSRS + NUM_VMX_MSRS)
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#else
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#define NUM_GUEST_MSRS (NUM_WORLD_MSRS + NUM_COMMON_MSRS)
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#define CAT_MSR_START_INDEX (NUM_WORLD_MSRS + NUM_COMMON_MSRS)
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#endif
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#else
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#define NUM_VCAT_MSRS 0U
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#endif
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/* For detailed layout of the emulated guest MSRs, see emulated_guest_msrs[NUM_GUEST_MSRS] in vmsr.c */
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#ifdef CONFIG_NVMX_ENABLED
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#define NUM_GUEST_MSRS (NUM_WORLD_MSRS + NUM_COMMON_MSRS + NUM_VMX_MSRS + NUM_VCAT_MSRS)
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#else
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#define NUM_GUEST_MSRS (NUM_WORLD_MSRS + NUM_COMMON_MSRS + NUM_VCAT_MSRS)
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#endif
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#define EOI_EXIT_BITMAP_SIZE 256U
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@ -617,6 +617,7 @@ static inline bool is_x2apic_msr(uint32_t msr)
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struct acrn_vcpu;
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void init_msr_emulation(struct acrn_vcpu *vcpu);
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void init_intercepted_cat_msr_list(void);
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uint32_t vmsr_get_guest_msr_index(uint32_t msr);
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void update_msr_bitmap_x2apic_apicv(struct acrn_vcpu *vcpu);
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void update_msr_bitmap_x2apic_passthru(struct acrn_vcpu *vcpu);
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