diff --git a/misc/vm_configs/boards/whl-ipc-i7/board.c b/misc/vm_configs/boards/whl-ipc-i7/board.c new file mode 100644 index 000000000..59edd23d3 --- /dev/null +++ b/misc/vm_configs/boards/whl-ipc-i7/board.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: American Megatrends Inc. + * Version: WL10R104 + * Release Date: 09/12/2019 + * BIOS Revision: 5.13 + * + * Base Board Information + * Manufacturer: Maxtang + * Product Name: WL10 + * Version: V1.0 + */ + +#include +#include +#include +#include + +static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = { + { + .type = DRHD0_DEVSCOPE0_TYPE, + .id = DRHD0_DEVSCOPE0_ID, + .bus = DRHD0_DEVSCOPE0_BUS, + .devfun = DRHD0_DEVSCOPE0_PATH, + }, +}; + +static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = { + { + .type = DRHD1_DEVSCOPE0_TYPE, + .id = DRHD1_DEVSCOPE0_ID, + .bus = DRHD1_DEVSCOPE0_BUS, + .devfun = DRHD1_DEVSCOPE0_PATH, + }, + { + .type = DRHD1_DEVSCOPE1_TYPE, + .id = DRHD1_DEVSCOPE1_ID, + .bus = DRHD1_DEVSCOPE1_BUS, + .devfun = DRHD1_DEVSCOPE1_PATH, + }, +}; + +static struct dmar_drhd drhd_info_array[DRHD_COUNT] = { + { + .dev_cnt = DRHD0_DEV_CNT, + .segment = DRHD0_SEGMENT, + .flags = DRHD0_FLAGS, + .reg_base_addr = DRHD0_REG_BASE, + .ignore = DRHD0_IGNORE, + .devices = drhd0_dev_scope + }, + { + .dev_cnt = DRHD1_DEV_CNT, + .segment = DRHD1_SEGMENT, + .flags = DRHD1_FLAGS, + .reg_base_addr = DRHD1_REG_BASE, + .ignore = DRHD1_IGNORE, + .devices = drhd1_dev_scope + }, +}; + +struct dmar_info plat_dmar_info = { + .drhd_count = DRHD_COUNT, + .drhd_units = drhd_info_array, +}; + +#ifdef CONFIG_RDT_ENABLED +struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM]; +struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES]; +#endif + +static const struct cpu_cx_data board_cpu_cx[3] = { + {{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */ + {{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x33UL}, 0x02U, 0x97U, 0x00U}, /* C2 */ + {{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x60UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */ +}; + +static const struct cpu_px_data board_cpu_px[10] = { + {0x835UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002E00UL, 0x002E00UL}, /* P0 */ + {0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL}, /* P1 */ + {0x7D0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001400UL, 0x001400UL}, /* P2 */ + {0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P3 */ + {0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P4 */ + {0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P5 */ + {0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P6 */ + {0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P7 */ + {0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P8 */ + {0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */ +}; + +const struct cpu_state_table board_cpu_state_tbl = { + "Intel(R) Core(TM) i7-8565U CPU @ 1.80GHz", + {(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px, + (uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx} +}; +const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; + +const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM]; diff --git a/misc/vm_configs/boards/whl-ipc-i7/board_info.h b/misc/vm_configs/boards/whl-ipc-i7/board_info.h new file mode 100644 index 000000000..38c8417e8 --- /dev/null +++ b/misc/vm_configs/boards/whl-ipc-i7/board_info.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_INFO_H +#define BOARD_INFO_H + +#define MAX_PCPU_NUM 4U +#define MAX_PLATFORM_CLOS_NUM 0U +#define MAX_MBA_CLOS_NUM_ENTRIES 0U +#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U +#define MAX_HIDDEN_PDEVS_NUM 0U + +#define HI_MMIO_START ~0UL +#define HI_MMIO_END 0UL +#define HI_MMIO_SIZE 0x0UL + +#endif /* BOARD_INFO_H */ diff --git a/misc/vm_configs/boards/whl-ipc-i7/pci_devices.h b/misc/vm_configs/boards/whl-ipc-i7/pci_devices.h new file mode 100644 index 000000000..d30d3c7c3 --- /dev/null +++ b/misc/vm_configs/boards/whl-ipc-i7/pci_devices.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: American Megatrends Inc. + * Version: WL10R104 + * Release Date: 09/12/2019 + * BIOS Revision: 5.13 + * + * Base Board Information + * Manufacturer: Maxtang + * Product Name: WL10 + * Version: V1.0 + */ + +#ifndef PCI_DEVICES_H_ +#define PCI_DEVICES_H_ + +#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U} + +#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U} + +#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U} + +#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U} + +#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U} + +#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U} + +#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U} + +#define SD_HOST_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U} + +#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U} + +#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x04U} + +#define PCI_BRIDGE_2 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U} + +#define PCI_BRIDGE_3 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x01U} + +#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U} + +#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U} + +#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U} + +#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U} + +#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U} + +#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x00U} + +#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U} + +#endif /* PCI_DEVICES_H_ */ diff --git a/misc/vm_configs/boards/whl-ipc-i7/platform_acpi_info.h b/misc/vm_configs/boards/whl-ipc-i7/platform_acpi_info.h new file mode 100644 index 000000000..bf6b1c3e5 --- /dev/null +++ b/misc/vm_configs/boards/whl-ipc-i7/platform_acpi_info.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING! + */ + +#ifndef PLATFORM_ACPI_INFO_H +#define PLATFORM_ACPI_INFO_H + +/* + * BIOS Information + * Vendor: American Megatrends Inc. + * Version: WL10R104 + * Release Date: 09/12/2019 + * BIOS Revision: 5.13 + * + * Base Board Information + * Manufacturer: Maxtang + * Product Name: WL10 + * Version: V1.0 + */ + +/* pm sstate data */ +#define PM1A_EVT_ADDRESS 0x1800UL +#define PM1A_EVT_ACCESS_SIZE 0x2U +#define PM1A_CNT_ADDRESS 0x1804UL + /* S3 is not supported by BIOS */ + +#undef S3_PKG_VAL_PM1A +#define S3_PKG_VAL_PM1A 0x0U + +#define WAKE_VECTOR_32 0x8C8AA08CUL +#define WAKE_VECTOR_64 0x8C8AA098UL + +#define RESET_REGISTER_ADDRESS 0xCF9UL +#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO +#define RESET_REGISTER_VALUE 0x6U + +/* DRHD of DMAR */ +#define DRHD_COUNT 2U + +#define DRHD0_DEV_CNT 0x1U +#define DRHD0_SEGMENT 0x0U +#define DRHD0_FLAGS 0x0U +#define DRHD0_REG_BASE 0xFED90000UL +#define DRHD0_IGNORE true +#define DRHD0_DEVSCOPE0_TYPE 0x1U +#define DRHD0_DEVSCOPE0_ID 0x0U +#define DRHD0_DEVSCOPE0_BUS 0x0U +#define DRHD0_DEVSCOPE0_PATH 0x10U + +#define DRHD1_DEV_CNT 0x2U +#define DRHD1_SEGMENT 0x0U +#define DRHD1_FLAGS 0x1U +#define DRHD1_REG_BASE 0xFED91000UL +#define DRHD1_IGNORE false +#define DRHD1_DEVSCOPE0_TYPE 0x3U +#define DRHD1_DEVSCOPE0_ID 0x2U +#define DRHD1_DEVSCOPE0_BUS 0x0U +#define DRHD1_DEVSCOPE0_PATH 0xf7U +#define DRHD1_DEVSCOPE1_TYPE 0x4U +#define DRHD1_DEVSCOPE1_ID 0x0U +#define DRHD1_DEVSCOPE1_BUS 0x0U +#define DRHD1_DEVSCOPE1_PATH 0xf6U + +/* PCI mmcfg base of MCFG */ +#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + +#endif /* PLATFORM_ACPI_INFO_H */ diff --git a/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h new file mode 100644 index 000000000..f9694e702 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define SOS_ROOTFS "root=/dev/sda3 " +#define SOS_CONSOLE "console=ttyS0 " +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 3U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=tty0 " \ + "consoleblank=0 " \ + "no_timer_check " \ + "quiet " \ + "loglevel=3 " \ + "i915.nuclear_pageflip=1 " \ + "hvlog=2M@0xe00000 " \ + "memmap=0x200000$0xe00000" + +#endif /* MISC_CFG_H */ diff --git a/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/pci_dev.c b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/pci_dev.c new file mode 100644 index 000000000..79033ec6b --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/pci_dev.c @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include diff --git a/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/vbar_base.h b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/vbar_base.h new file mode 100644 index 000000000..d9a05b701 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/vbar_base.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xa0000000UL, \ + .vbar_base[2] = 0x90000000UL + +#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141e000UL + +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1400000UL + +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0xa1416000UL, \ + .vbar_base[2] = 0xa141d000UL + +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141c000UL + +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1414000UL, \ + .vbar_base[1] = 0xa141b000UL, \ + .vbar_base[5] = 0xa141a000UL + +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1419000UL + +#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xa1410000UL, \ + .vbar_base[4] = 0xa1000000UL + +#define SMBUS_0_VBAR .vbar_base[0] = 0xa1418000UL + +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0xfe010000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1300000UL + +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1200000UL, \ + .vbar_base[3] = 0xa1220000UL + +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1100000UL, \ + .vbar_base[3] = 0xa1120000UL + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/whl-ipc-i7.config b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/whl-ipc-i7.config new file mode 100644 index 000000000..9dfacdc68 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid/whl-ipc-i7/whl-ipc-i7.config @@ -0,0 +1,37 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="whl-ipc-i7" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x9600000 +CONFIG_PLATFORM_RAM_SIZE=0x400000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x400000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_GPU_SBDF=0x00000010 +CONFIG_UEFI_OS_LOADER_NAME="" +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=64 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_LEGACY=y +CONFIG_SERIAL_PIO_BASE=0x3F8 +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h b/misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h new file mode 100644 index 000000000..f9694e702 --- /dev/null +++ b/misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define SOS_ROOTFS "root=/dev/sda3 " +#define SOS_CONSOLE "console=ttyS0 " +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 3U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=tty0 " \ + "consoleblank=0 " \ + "no_timer_check " \ + "quiet " \ + "loglevel=3 " \ + "i915.nuclear_pageflip=1 " \ + "hvlog=2M@0xe00000 " \ + "memmap=0x200000$0xe00000" + +#endif /* MISC_CFG_H */ diff --git a/misc/vm_configs/scenarios/industry/whl-ipc-i7/pci_dev.c b/misc/vm_configs/scenarios/industry/whl-ipc-i7/pci_dev.c new file mode 100644 index 000000000..79033ec6b --- /dev/null +++ b/misc/vm_configs/scenarios/industry/whl-ipc-i7/pci_dev.c @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include diff --git a/misc/vm_configs/scenarios/industry/whl-ipc-i7/vbar_base.h b/misc/vm_configs/scenarios/industry/whl-ipc-i7/vbar_base.h new file mode 100644 index 000000000..9077629d8 --- /dev/null +++ b/misc/vm_configs/scenarios/industry/whl-ipc-i7/vbar_base.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/vm_configs/scenarios/industry/whl-ipc-i7/whl-ipc-i7.config b/misc/vm_configs/scenarios/industry/whl-ipc-i7/whl-ipc-i7.config new file mode 100644 index 000000000..543fb3a2c --- /dev/null +++ b/misc/vm_configs/scenarios/industry/whl-ipc-i7/whl-ipc-i7.config @@ -0,0 +1,37 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="whl-ipc-i7" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x14800000 +CONFIG_PLATFORM_RAM_SIZE=0x400000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x400000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_GPU_SBDF=0x00000010 +CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi" +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=64 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_LEGACY=y +CONFIG_SERIAL_PIO_BASE=0x3F8 +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h new file mode 100644 index 000000000..280006bb7 --- /dev/null +++ b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#endif /* MISC_CFG_H */ diff --git a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/pci_dev.c b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/pci_dev.c new file mode 100644 index 000000000..1fc1b2de2 --- /dev/null +++ b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/pci_dev.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR + +struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = { + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}, + .vdev_ops = &vhostbridge_ops, + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U}, + PTDEV(SATA_CONTROLLER_0), + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, + PTDEV(ETHERNET_CONTROLLER_0), + }, +}; + +struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = { + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}, + .vdev_ops = &vhostbridge_ops, + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U}, + PTDEV(USB_CONTROLLER_0), + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, + PTDEV(ETHERNET_CONTROLLER_1), + }, +}; diff --git a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/vbar_base.h b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/vbar_base.h new file mode 100644 index 000000000..d9a05b701 --- /dev/null +++ b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/vbar_base.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xa0000000UL, \ + .vbar_base[2] = 0x90000000UL + +#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141e000UL + +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1400000UL + +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0xa1416000UL, \ + .vbar_base[2] = 0xa141d000UL + +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xa141c000UL + +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1414000UL, \ + .vbar_base[1] = 0xa141b000UL, \ + .vbar_base[5] = 0xa141a000UL + +#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1419000UL + +#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xa1410000UL, \ + .vbar_base[4] = 0xa1000000UL + +#define SMBUS_0_VBAR .vbar_base[0] = 0xa1418000UL + +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0xfe010000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1300000UL + +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1200000UL, \ + .vbar_base[3] = 0xa1220000UL + +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1100000UL, \ + .vbar_base[3] = 0xa1120000UL + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/whl-ipc-i7.config b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/whl-ipc-i7.config new file mode 100644 index 000000000..208b365e0 --- /dev/null +++ b/misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/whl-ipc-i7.config @@ -0,0 +1,37 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="whl-ipc-i7" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x7800000 +CONFIG_PLATFORM_RAM_SIZE=0x400000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x400000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_GPU_SBDF=0x00000010 +CONFIG_UEFI_OS_LOADER_NAME="" +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=64 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_LEGACY=y +CONFIG_SERIAL_PIO_BASE=0x3F8 +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3