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acrn-hypervisor
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HV Cx: load cx data to boot_cpu_data when boot 

The cx data is hardcoded within HV, load it to boot_cpu_data when HV boot.
The patch provide a3960 soc cx data for example.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
This commit is contained in:
Victor Sun 2018-04-17 13:52:00 +08:00 committed by Jack Ren
parent d63b9002dd
commit 373a828058
3 changed files with 56 additions and 4 deletions
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24
hypervisor/arch/x86/cpu_state_tbl.c
View File

@ -53,6 +53,13 @@ struct cpu_px_data px_a3960[] = {
{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P16 */
};
/* The table includes cpu cx info of Intel A3960 SoC */
struct cpu_cx_data cx_a3960[] = {
{{SPACE_FFixedHW, 0x0, 0, 0, 0}, 0x1, 0x1, 0x3E8}, /* C1 */
{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x415}, 0x2, 0x32, 0x0A}, /* C2 */
{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A} /* C3 */
};
/* The table includes cpu px info of Intel J3455 SoC */
struct cpu_px_data px_j3455[] = {
{0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */
@ -71,10 +78,12 @@ struct cpu_state_table {
struct cpu_state_info state_info;
} cpu_state_tbl[] = {
{"Intel(R) Atom(TM) Processor A3960 @ 1.90GHz",
{ARRAY_SIZE(px_a3960), px_a3960}
{ARRAY_SIZE(px_a3960), px_a3960,
ARRAY_SIZE(cx_a3960), cx_a3960}
},
{"Intel(R) Celeron(R) CPU J3455 @ 1.50GHz",
{ARRAY_SIZE(px_j3455), px_j3455}
{ARRAY_SIZE(px_j3455), px_j3455,
0, NULL}
}
};
@ -122,4 +131,15 @@ void load_cpu_state_data(void)
boot_cpu_data.state_info.px_data = state_info->px_data;
}
if (state_info->cx_cnt && state_info->cx_data) {
if (state_info->cx_cnt > MAX_CX_ENTRY) {
boot_cpu_data.state_info.cx_cnt = MAX_CX_ENTRY;
} else {
boot_cpu_data.state_info.cx_cnt = state_info->cx_cnt;
}
boot_cpu_data.state_info.cx_data = state_info->cx_data;
}
}

12
hypervisor/include/arch/x86/cpu.h
View File

@ -236,8 +236,10 @@ enum feature_word {
};
struct cpu_state_info {
uint8_t px_cnt;
uint8_t px_cnt; /* count of all Px states */
struct cpu_px_data *px_data;
uint8_t cx_cnt; /* count of all Cx entries */
struct cpu_cx_data *cx_data;
};
struct cpuinfo_x86 {
@ -254,7 +256,13 @@ struct cpuinfo_x86 {
extern struct cpuinfo_x86 boot_cpu_data;
#define MAX_PSTATE 20
#define MAX_PSTATE 20 /* max num of supported Px count */
#define MAX_CSTATE 8 /* max num of supported Cx count */
/* We support MAX_CSTATE num of Cx, means have (MAX_CSTATE - 1) Cx entries,
* i.e. supported Cx entry index range from 1 to MAX_CX_ENTRY.
*/
#define MAX_CX_ENTRY (MAX_CSTATE - 1)
/* Function prototypes */
void cpu_dead(uint32_t logical_id);

24
hypervisor/include/public/acrn_common.h
View File

@ -292,6 +292,30 @@ struct acrn_vm_pci_msix_remap {
* @brief Info The power state data of a VCPU.
*
*/
#define SPACE_SYSTEM_MEMORY 0
#define SPACE_SYSTEM_IO 1
#define SPACE_PCI_CONFIG 2
#define SPACE_Embedded_Control 3
#define SPACE_SMBUS 4
#define SPACE_PLATFORM_COMM 10
#define SPACE_FFixedHW 0x7F
struct acrn_register {
uint8_t space_id;
uint8_t bit_width;
uint8_t bit_offset;
uint8_t access_size;
uint64_t address;
} __attribute__((aligned(8)));
struct cpu_cx_data {
struct acrn_register cx_reg;
uint8_t type;
uint32_t latency;
uint64_t power;
} __attribute__((aligned(8)));
struct cpu_px_data {
uint64_t core_frequency; /* megahertz */
uint64_t power; /* milliWatts */