Doc: Grammatical/style edits to split device model page

Signed-off-by: Deb Taylor <deb.taylor@intel.com>
This commit is contained in:
Deb Taylor 2020-03-29 22:10:55 -04:00 committed by deb-intel
parent 86aa338a5f
commit 37291fa890
2 changed files with 23 additions and 22 deletions

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@ -155,10 +155,10 @@ directly. EPT mapping is not built for these pages having MSI-X table.
Device configuration emulation
******************************
PCI configuration space could been accessed by PCI-compatible Configuration Mechanism
(IO port 0xCF8/CFC) and PCI Express Enhanced Configuration Access Mechanism (PCI MMCONFIG).
ACRN hypervisor will trap these PCI configuration space access and emulate it. You may refer
to :ref:`split-device-model` for detail.
The PCI configuration space can be accessed by a PCI-compatible
Configuration Mechanism (IO port 0xCF8/CFC) and the PCI Express Enhanced
Configuration Access Mechanism (PCI MMCONFIG). The ACRN hypervisor traps
this PCI configuration space access and emulate it. Refer to :ref:`split-device-model` for details.
MSI-X table emulation
*********************
@ -223,7 +223,7 @@ Remapping of (virtual) PIC interrupts are set up in a similar sequence:
Initialization of remapping of virtual MSI for Service VM
This figure illustrates how mappings of MSI or MSIX are set up for
This figure illustrates how mappings of MSI or MSIX are set up for
Service VM. Service VM is responsible for issuing a hypercall to notify the
hypervisor before it configures the PCI configuration space to enable an
MSI. The hypervisor takes this opportunity to set up a remapping for the

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@ -3,34 +3,35 @@
Split Device Model
==================
We usually emulate device in Device Model. However, we need to emulate device in
ACRN Hypervisor for some reasons. For example, post-launched RTVM needs to emulate
pass through PCI(e) devices in ACRN Hypervisor in which case it could continue to
running even if the Device Model is killed. In spite of this, the Device Model still
should own the overall resouce management like memroy/MMIO space, interrupt pin etc.
So there shall be one communication method provided by ACRN Hypervisor, which used
to align the resource information for Device Model to ACRN Hypervisor emulated device.
We usually emulate devices in the Device Model. However, in some cases, we
need to emulate devices in the ACRN Hypervisor. For example, the
post-launched RTVM needs to emulate passthrough PCI(e) devices in the ACRN
Hypervisor so that it can continue to run even if the Device Model is
no longer working. In spite of this, the Device Model still owns the overall
resource management such as memory/MMIO space, interrupt pin, etc.
Let's still take the pass through PCI(e) device as an example:
Before we split pass through PCI(e) device from Device Model to ACRN Hypervisor, the
whole picture is like this:
One communication method provided by the ACRN Hypervisor aligns the resource information for the Device Model with the ACRN Hypervisor emulated device.
Let's take the passthrough PCI(e) device as an example. Before we split
passthrough PCI(e) devices from the Device Model to the ACRN Hypervisor, the
whole picture looks like this:
.. figure:: images/split-dm-image1.png
:align: center
:width: 900px
:name: split-dm-architecture-overview1
PCI Config space access in Service VM or Pre-launched VM
PCI Config space access in the Service VM or Pre-launched VM
.. figure:: images/split-dm-image2.png
:align: center
:width: 900px
:name: split-dm-architecture-overview2
PCI Config space access in Post-launched VM
PCI Config space access in the Post-launched VM
After we split pass through PCI(e) device from Device Model to ACRN Hypervisor, the
whole picture is like this:
After we split passthrough PCI(e) devices from the Device Model to the
ACRN Hypervisor, the whole picture looks like this:
.. figure:: images/split-dm-image3.png
:align: center
@ -42,13 +43,13 @@ whole picture is like this:
:width: 900px
:name: split-dm-architecture-overview4
PCI Config space access in Post-launched VM
PCI Config space access in the Post-launched VM
Interfaces Design
=================
In order to achieve this, we add a new pair of hypercall to align the PCI(e) BAR
and INTx information.
In order to achieve this, we have added a new pair of hypercalls to align
the PCI(e) BAR and INTx information.
.. doxygenfunction:: hcall_assign_pcidev
:project: Project ACRN