hv: Pass address of vioapic struct to register_mmio_emulation_handler
Changes the mmio handler data from that of the acrn_vm struct to the acrn_vioapic. Add nr_pins and base_addr to the acrn_vioapic data structure. Tracked-On: #4151 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
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dd6c80c305
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@ -92,7 +92,7 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, uint32_t level)
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uint32_t old_lvl;
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union ioapic_rte rte;
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if (pin < REDIR_ENTRIES_HW) {
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if (pin < vioapic->nr_pins) {
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rte = vioapic->rtbl[pin];
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old_lvl = (uint32_t)bitmap_test((uint16_t)(pin & 0x3FU), &vioapic->pin_state[pin >> 6U]);
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if (level == 0U) {
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@ -232,11 +232,9 @@ static inline bool vioapic_need_intr(const struct acrn_vioapic *vioapic, uint16_
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{
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uint32_t lvl;
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union ioapic_rte rte;
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bool ret;
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bool ret = false;
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if (pin >= REDIR_ENTRIES_HW) {
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ret = false;
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} else {
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if (pin < vioapic->nr_pins) {
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rte = vioapic->rtbl[pin];
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lvl = (uint32_t)bitmap_test(pin & 0x3FU, &vioapic->pin_state[pin >> 6U]);
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ret = !!(((rte.bits.intr_polarity == IOAPIC_RTE_INTPOL_ALO) && lvl == 0U) ||
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@ -359,7 +357,7 @@ vioapic_mmio_rw(struct acrn_vioapic *vioapic, uint64_t gpa,
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uint32_t offset;
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uint64_t rflags;
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offset = (uint32_t)(gpa - VIOAPIC_BASE);
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offset = (uint32_t)(gpa - vioapic->base_addr);
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spinlock_irqsave_obtain(&(vioapic->mtx), &rflags);
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@ -466,30 +464,29 @@ vioapic_init(struct acrn_vm *vm)
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vm->arch_vm.vioapic.vm = vm;
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spinlock_init(&(vm->arch_vm.vioapic.mtx));
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vm->arch_vm.vioapic.base_addr = VIOAPIC_BASE;
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if (is_sos_vm(vm)) {
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vm->arch_vm.vioapic.nr_pins = REDIR_ENTRIES_HW;
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} else {
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vm->arch_vm.vioapic.nr_pins = VIOAPIC_RTE_NUM;
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}
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vioapic_reset(vm);
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register_mmio_emulation_handler(vm,
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vioapic_mmio_access_handler,
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(uint64_t)VIOAPIC_BASE,
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(uint64_t)VIOAPIC_BASE + VIOAPIC_SIZE,
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vm, false);
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(uint64_t)vm->arch_vm.vioapic.base_addr,
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(uint64_t)vm->arch_vm.vioapic.base_addr + VIOAPIC_SIZE,
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(void *)&vm->arch_vm.vioapic, false);
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ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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(uint64_t)VIOAPIC_BASE, (uint64_t)VIOAPIC_SIZE);
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(uint64_t)vm->arch_vm.vioapic.base_addr, VIOAPIC_SIZE);
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vm->arch_vm.vioapic.ready = true;
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}
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uint32_t
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vioapic_pincount(const struct acrn_vm *vm)
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{
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uint32_t ret;
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if (is_sos_vm(vm)) {
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ret = REDIR_ENTRIES_HW;
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} else {
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ret = VIOAPIC_RTE_NUM;
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}
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return ret;
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return vm->arch_vm.vioapic.nr_pins;
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}
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/*
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@ -498,14 +495,11 @@ vioapic_pincount(const struct acrn_vm *vm)
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*/
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int32_t vioapic_mmio_access_handler(struct io_request *io_req, void *handler_private_data)
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{
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struct acrn_vm *vm = (struct acrn_vm *)handler_private_data;
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struct acrn_vioapic *vioapic;
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struct acrn_vioapic *vioapic = (struct acrn_vioapic *)handler_private_data;
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struct mmio_request *mmio = &io_req->reqs.mmio;
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uint64_t gpa = mmio->address;
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int32_t ret = 0;
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vioapic = vm_ioapic(vm);
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/* Note all RW to IOAPIC are 32-Bit in size */
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if (mmio->size == 4UL) {
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uint32_t data = (uint32_t)mmio->value;
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@ -51,6 +51,8 @@
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struct acrn_vioapic {
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struct acrn_vm *vm;
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spinlock_t mtx;
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uint32_t base_addr;
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uint32_t nr_pins;
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uint32_t id;
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bool ready;
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uint32_t ioregsel;
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