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acrn-config: code refactoring for CAT/MBA 

1.Modify clos_mask and mba_delay as a member of the union type.
2.Move HV_SUPPORTED_MAX_CLOS ,MAX_CACHE_CLOS_NUM_ENTRIES and
MAX_MBA_CLOS_NUM_ENTRIES to misc_cfg.h file.

Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
Wei Liu 2020-08-23 17:05:46 -07:00 committed by wenlingz
parent 7eb103478a
commit 29ac258134
20 changed files with 272 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hypervisor/arch/x86/rdt.c
View File

@ -22,9 +22,9 @@ const uint16_t hv_clos = 0U;
* clos value (valid_clos_num) that is common between the resources as
* each resource's clos max value to have consistent allocation.
*/
#ifdef CONFIG_RDT_ENABLED
uint16_t valid_clos_num = HV_SUPPORTED_MAX_CLOS;
#ifdef CONFIG_RDT_ENABLED
static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
[RDT_RESOURCE_L3] = {
.res.cache = {
@ -35,7 +35,7 @@ static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
.clos_max = 0U,
.res_id = RDT_RESID_L3,
.msr_base = MSR_IA32_L3_MASK_BASE,
.platform_clos_array = platform_l3_clos_array,
.platform_clos_array = platform_l3_clos_array,
},
[RDT_RESOURCE_L2] = {
.res.cache = {
@ -56,7 +56,7 @@ static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
.clos_max = 0U,
.res_id = RDT_RESID_MBA,
.msr_base = MSR_IA32_MBA_MASK_BASE,
.platform_clos_array = platform_mba_clos_array,
.platform_clos_array = platform_mba_clos_array,
},
};
@ -78,11 +78,11 @@ static void init_cat_capability(int res)
#ifdef CONFIG_CDP_ENABLED
res_cap_info[res].res.cache.is_cdp_enabled = ((ecx & 0x4U) != 0U);
#else
res_cap_info[res].res.cache.is_cdp_enabled = false;
res_cap_info[res].res.cache.is_cdp_enabled = false;
#endif
if (res_cap_info[res].res.cache.is_cdp_enabled) {
res_cap_info[res].clos_max = (uint16_t)((edx & 0xffffU) >> 1U) + 1U;
/* enable CDP before setting COS to simplify CAT mask rempping
/* enable CDP before setting COS to simplify CAT mask remapping
* and prevent unintended behavior.
*/
msr_write(res_cap_info[res].res.cache.msr_qos_cfg, 0x1UL);
@ -107,7 +107,7 @@ static void init_mba_capability(int res)
}
/*
* @pre valid_clos_num > 0U
* @pre valid_clos_num > 0U
*/
void init_rdt_info(void)
{
@ -148,7 +148,7 @@ void init_rdt_info(void)
/*
* @pre res < RDT_NUM_RESOURCES
* @pre res_clos_info[i].mba_delay <= res_cap_info[res].res.membw.mba_max
* @pre length of res_clos_info[i].clos_mask <= cbm_len && all 1's in clos_mask is continuous
* @pre length of res_clos_info[i].clos_mask <= cbm_len && all 1's in clos_mask is continuous
*/
static void setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_clos_info *res_clos_info)
{
@ -163,10 +163,10 @@ static void setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_c
switch (res) {
case RDT_RESOURCE_L3:
case RDT_RESOURCE_L2:
val = (uint64_t)res_clos_info[i].clos_mask;
val = (uint64_t)res_clos_info[i].value.clos_mask;
break;
case RDT_RESOURCE_MBA:
val = (uint64_t)res_clos_info[i].mba_delay;
val = (uint64_t)res_clos_info[i].value.mba_delay;
break;
default:
ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res);

13
hypervisor/include/arch/x86/board.h
View File

@ -10,13 +10,16 @@
#include <board_info.h>
#include <host_pm.h>
#include <pci.h>
#include <misc_cfg.h>
/* forward declarations */
struct acrn_vm;
struct platform_clos_info {
uint16_t mba_delay;
uint32_t clos_mask;
union {
uint16_t mba_delay;
uint32_t clos_mask;
}value;
uint32_t msr_index;
};
@ -28,9 +31,9 @@ struct vmsix_on_msi_info {
extern struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
extern struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
extern struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
extern struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
extern struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
extern struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
extern struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
extern const struct cpu_state_table board_cpu_state_tbl;

4
misc/hv_prebuild/vm_cfg_checks.c
View File

@ -76,6 +76,7 @@ static bool check_vm_uuid_collision(uint16_t vm_id)
return ret;
}
#ifdef CONFIG_RDT_ENABLED
static bool check_vm_clos_config(uint16_t vm_id)
{
uint16_t i;
@ -95,6 +96,7 @@ static bool check_vm_clos_config(uint16_t vm_id)
}
return ret;
}
#endif
/**
* @pre vm_config != NULL
@ -157,9 +159,11 @@ bool sanitize_vm_config(void)
}
}
#ifdef CONFIG_RDT_ENABLED
if (ret) {
ret = check_vm_clos_config(vm_id);
}
#endif
if (ret &&
(((vm_config->epc.size | vm_config->epc.base) & ~PAGE_MASK) != 0UL)) {

6
misc/vm_configs/boards/nuc7i7dnb/board.c
View File

@ -71,9 +71,9 @@ struct dmar_info plat_dmar_info = {
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
static const struct cpu_cx_data board_cpu_cx[3] = {

1
misc/vm_configs/boards/nuc7i7dnb/board_info.h
View File

@ -8,7 +8,6 @@
#define BOARD_INFO_H
#define MAX_PCPU_NUM 4U
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
#define MAX_HIDDEN_PDEVS_NUM 0U

6
misc/vm_configs/boards/whl-ipc-i5/board.c
View File

@ -72,9 +72,9 @@ struct dmar_info plat_dmar_info = {
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
static const struct cpu_cx_data board_cpu_cx[3] = {

1
misc/vm_configs/boards/whl-ipc-i5/board_info.h
View File

@ -8,7 +8,6 @@
#define BOARD_INFO_H
#define MAX_PCPU_NUM 4U
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
#define MAX_HIDDEN_PDEVS_NUM 0U

6
misc/vm_configs/boards/whl-ipc-i7/board.c
View File

@ -72,9 +72,9 @@ struct dmar_info plat_dmar_info = {
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
static const struct cpu_cx_data board_cpu_cx[3] = {

1
misc/vm_configs/boards/whl-ipc-i7/board_info.h
View File

@ -8,7 +8,6 @@
#define BOARD_INFO_H
#define MAX_PCPU_NUM 4U
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
#define MAX_HIDDEN_PDEVS_NUM 0U

22
misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h
View File

@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/hybrid/whl-ipc-i5/misc_cfg.h
View File

@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h
View File

@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h
View File

@ -25,6 +25,28 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#define VM0_PASSTHROUGH_TPM
#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
#define VM0_TPM_BUFFER_SIZE 0x5000UL

22
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h
View File

@ -25,6 +25,28 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#define VM0_PASSTHROUGH_TPM
#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
#define VM0_TPM_BUFFER_SIZE 0x5000UL

22
misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h
View File

@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/industry/whl-ipc-i5/misc_cfg.h
View File

@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h
View File

@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h
View File

@ -7,4 +7,26 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/misc_cfg.h
View File

@ -7,4 +7,26 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h
View File

@ -7,4 +7,26 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */