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hv: vioapic: remove EOI register support 

The IOAPIC specification defined EOI register for 0x20 version. The
original vioapic code implemented this register but the version was
still export as 0x11.

Tried to set 0x20, the Linux kernel has't access this EOI register,
still rely on lapic to send eoi.

From Linux ioapic driver comments, it says that only send EOI via EOI
register when met IOAPIC hardware bug.

This patch removes all 0x20 IOAPIC code to reduce the code size.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yu Wang 2018-08-02 09:58:24 +00:00 committed by lijinxia
parent f96f048f71
commit 1e1886794e
2 changed files with 3 additions and 43 deletions
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45
hypervisor/arch/x86/guest/vioapic.c
View File

@ -37,6 +37,7 @@
#define NEED_TMR_UPDATE (~(IOAPIC_RTE_INTMASK | IOAPIC_RTE_INTPOL))
#define ACRN_DBG_IOAPIC 6U
#define ACRN_IOAPIC_VERSION 0x11U
struct vioapic {
struct vm *vm;
@ -248,7 +249,8 @@ vioapic_indirect_read(struct vioapic *vioapic, uint32_t addr)
case IOAPIC_ID:
return vioapic->id;
case IOAPIC_VER:
return (((uint32_t)pincount - 1U) << MAX_RTE_SHIFT) | 0x11U;
return (((uint32_t)pincount - 1U) << MAX_RTE_SHIFT) |
ACRN_IOAPIC_VERSION;
case IOAPIC_ARB:
return vioapic->id;
default:
@ -271,42 +273,6 @@ vioapic_indirect_read(struct vioapic *vioapic, uint32_t addr)
return 0;
}
/*
* version 0x20+ ioapic has EOI register. And cpu could write vector to this
* register to clear related IRR.
* Due to the race between vcpus, ensure to do VIOAPIC_LOCK(vioapic) &
* VIOAPIC_UNLOCK(vioapic) by caller.
*/
static void
vioapic_write_eoi(struct vioapic *vioapic, uint32_t vector)
{
struct vm *vm = vioapic->vm;
union ioapic_rte rte;
uint32_t pin, pincount;
if (vector < VECTOR_FOR_INTR_START || vector > NR_MAX_VECTOR) {
pr_err("vioapic_process_eoi: invalid vector %u", vector);
}
pincount = vioapic_pincount(vm);
for (pin = 0U; pin < pincount; pin++) {
rte = vioapic->rtbl[pin];
if (((rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC) != vector) ||
((rte.full & IOAPIC_RTE_REM_IRR) == 0UL)) {
continue;
}
vioapic->rtbl[pin].full &= ~IOAPIC_RTE_REM_IRR;
if (vioapic->acnt[pin] > 0) {
dev_dbg(ACRN_DBG_IOAPIC,
"ioapic pin%hhu: asserted at eoi, acnt %d",
pin, vioapic->acnt[pin]);
vioapic_send_intr(vioapic, pin);
}
}
}
/* Due to the race between vcpus, ensure to do VIOAPIC_LOCK(vioapic) &
* VIOAPIC_UNLOCK(vioapic) by caller.
*/
@ -458,11 +424,6 @@ vioapic_mmio_rw(struct vioapic *vioapic, uint64_t gpa,
vioapic->ioregsel = *data & 0xFFU;
}
break;
case IOAPIC_EOIR:
if (!do_read) {
vioapic_write_eoi(vioapic, *data);
}
break;
case IOAPIC_WINDOW:
if (do_read) {
*data = vioapic_indirect_read(vioapic,

1
hypervisor/include/arch/x86/apicreg.h
View File

@ -451,7 +451,6 @@ union ioapic_rte {
/* window register offset */
#define IOAPIC_REGSEL 0x00U
#define IOAPIC_WINDOW 0x10U
#define IOAPIC_EOIR 0x40U
/* indexes into IO APIC */
#define IOAPIC_ID 0x00U