HV: modularization cleanup instr_emul header file
separate the private macro/structure/functions, which are just used in instr_emul.c; and move instr_emul.h to public include path. Tracked-On: #1842 Signed-off-by: Minggui Cao <minggui.cao@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
parent
18dbdfd5d7
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173b534b05
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@ -6,7 +6,7 @@
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#include <hypervisor.h>
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#include "guest/instr_emul.h"
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#include <instr_emul.h>
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#define ACRN_DBG_EPT 6U
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@ -29,8 +29,35 @@
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*/
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#include <hypervisor.h>
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#include <instr_emul.h>
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#include "instr_emul.h"
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#define CPU_REG_FIRST CPU_REG_RAX
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#define CPU_REG_LAST CPU_REG_GDTR
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#define CPU_REG_GENERAL_FIRST CPU_REG_RAX
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#define CPU_REG_GENERAL_LAST CPU_REG_R15
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#define CPU_REG_NONGENERAL_FIRST CPU_REG_CR0
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#define CPU_REG_NONGENERAL_LAST CPU_REG_GDTR
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#define CPU_REG_NATURAL_FIRST CPU_REG_CR0
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#define CPU_REG_NATURAL_LAST CPU_REG_RFLAGS
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#define CPU_REG_64BIT_FIRST CPU_REG_EFER
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#define CPU_REG_64BIT_LAST CPU_REG_PDPTE3
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#define CPU_REG_SEG_FIRST CPU_REG_ES
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#define CPU_REG_SEG_LAST CPU_REG_GS
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#define PSL_C 0x00000001U /* carry bit */
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#define PSL_PF 0x00000004U /* parity bit */
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#define PSL_AF 0x00000010U /* bcd carry bit */
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#define PSL_Z 0x00000040U /* zero bit */
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#define PSL_N 0x00000080U /* negative bit */
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#define PSL_D 0x00000400U /* string instruction direction bit */
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#define PSL_V 0x00000800U /* overflow bit */
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#define PSL_AC 0x00040000U /* alignment checking */
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/*
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* Protections are chosen from these bits, or-ed together
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*/
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#define PROT_READ 0x01U /* pages can be read */
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#define PROT_WRITE 0x02U /* pages can be written */
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/* struct vie_op.op_type */
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#define VIE_OP_TYPE_NONE 0U
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@ -192,6 +219,39 @@ struct vmcs_seg_field {
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uint32_t access_field;
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};
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/*
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* The 'access' field has the format specified in Table 21-2 of the Intel
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* Architecture Manual vol 3b.
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*
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* XXX The contents of the 'access' field are architecturally defined except
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* bit 16 - Segment Unusable.
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*/
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struct seg_desc {
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uint64_t base;
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uint32_t limit;
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uint32_t access;
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};
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static inline uint32_t seg_desc_type(uint32_t access)
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{
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return (access & 0x001fU);
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}
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static inline bool seg_desc_present(uint32_t access)
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{
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return ((access & 0x0080U) != 0U);
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}
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static inline bool seg_desc_def32(uint32_t access)
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{
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return ((access & 0x4000U) != 0U);
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}
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static inline bool seg_desc_unusable(uint32_t access)
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{
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return ((access & 0x10000U) != 0U);
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}
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static void encode_vmcs_seg_desc(enum cpu_reg_name seg,
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struct vmcs_seg_field *desc)
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{
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@ -1,200 +0,0 @@
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/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef INSTR_EMUL_WRAPPER_H
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#define INSTR_EMUL_WRAPPER_H
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#include <cpu.h>
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/**
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* Define the following MACRO to make range checking clear.
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*
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* CPU_REG_FIRST indicates the first register name, its value
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* is the same as CPU_REG_RAX;
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* CPU_REG_LAST indicates the last register name, its value is
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* the same as CPU_REG_GDTR;
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*
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* CPU_REG_GENERAL_FIRST indicates the first general register name,
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* its value is the same as CPU_REG_RAX;
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* CPU_REG_GENERAL_LAST indicates the last general register name,
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* its value is the same as CPU_REG_RDI;
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*
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* CPU_REG_NONGENERAL_FIRST indicates the first non general register
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* name, its value is the same as CPU_REG_CR0;
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* CPU_REG_NONGENERAL_LAST indicates the last non general register
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* name, its value is the same as CPU_REG_GDTR;
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*
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* CPU_REG_NATURAL_FIRST indicates the first register name that
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* is corresponds to the natural width field in VMCS, its value
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* is the same as CPU_REG_CR0;
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* CPU_REG_NATURAL_LAST indicates the last register name that
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* is corresponds to the natural width field in VMCS, its value
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* is the same as CPU_REG_RFLAGS;
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*
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* CPU_REG_64BIT_FIRST indicates the first register name that
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* is corresponds to the 64 bit field in VMCS, its value
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* is the same as CPU_REG_EFER;
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* CPU_REG_64BIT_LAST indicates the last register name that
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* is corresponds to the 64 bit field in VMCS, its value
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* is the same as CPU_REG_PDPTE3;
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*
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* CPU_REG_SEG_FIRST indicates the first segement register name,
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* its value is the same as CPU_REG_ES;
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* CPU_REG_SEG_FIRST indicates the last segement register name,
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* its value is the same as CPU_REG_GS
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*
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*/
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#define CPU_REG_FIRST CPU_REG_RAX
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#define CPU_REG_LAST CPU_REG_GDTR
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#define CPU_REG_GENERAL_FIRST CPU_REG_RAX
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#define CPU_REG_GENERAL_LAST CPU_REG_R15
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#define CPU_REG_NONGENERAL_FIRST CPU_REG_CR0
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#define CPU_REG_NONGENERAL_LAST CPU_REG_GDTR
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#define CPU_REG_NATURAL_FIRST CPU_REG_CR0
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#define CPU_REG_NATURAL_LAST CPU_REG_RFLAGS
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#define CPU_REG_64BIT_FIRST CPU_REG_EFER
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#define CPU_REG_64BIT_LAST CPU_REG_PDPTE3
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#define CPU_REG_SEG_FIRST CPU_REG_ES
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#define CPU_REG_SEG_LAST CPU_REG_GS
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struct instr_emul_vie_op {
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uint8_t op_type; /* type of operation (e.g. MOV) */
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uint16_t op_flags;
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};
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#define VIE_PREFIX_SIZE 4U
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#define VIE_INST_SIZE 15U
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struct instr_emul_vie {
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uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
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uint8_t num_valid; /* size of the instruction */
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uint8_t num_processed;
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uint8_t addrsize:4, opsize:4; /* address and operand sizes */
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uint8_t rex_w:1, /* REX prefix */
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rex_r:1,
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rex_x:1,
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rex_b:1,
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rex_present:1,
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repz_present:1, /* REP/REPE/REPZ prefix */
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repnz_present:1, /* REPNE/REPNZ prefix */
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opsize_override:1, /* Operand size override */
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addrsize_override:1, /* Address size override */
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seg_override:1; /* Segment override */
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uint8_t mod:2, /* ModRM byte */
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reg:4,
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rm:4;
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uint8_t ss:2, /* SIB byte */
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index:4,
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base:4;
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uint8_t disp_bytes;
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uint8_t imm_bytes;
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uint8_t scale;
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enum cpu_reg_name base_register; /* CPU_REG_xyz */
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enum cpu_reg_name index_register; /* CPU_REG_xyz */
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enum cpu_reg_name segment_register; /* CPU_REG_xyz */
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int64_t displacement; /* optional addr displacement */
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int64_t immediate; /* optional immediate operand */
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uint8_t decoded; /* set to 1 if successfully decoded */
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uint8_t opcode;
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struct instr_emul_vie_op op; /* opcode description */
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uint64_t dst_gpa; /* saved dst operand gpa. Only for movs */
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};
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#define PSL_C 0x00000001U /* carry bit */
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#define PSL_PF 0x00000004U /* parity bit */
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#define PSL_AF 0x00000010U /* bcd carry bit */
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#define PSL_Z 0x00000040U /* zero bit */
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#define PSL_N 0x00000080U /* negative bit */
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#define PSL_D 0x00000400U /* string instruction direction bit */
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#define PSL_V 0x00000800U /* overflow bit */
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#define PSL_AC 0x00040000U /* alignment checking */
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/*
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* The 'access' field has the format specified in Table 21-2 of the Intel
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* Architecture Manual vol 3b.
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*
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* XXX The contents of the 'access' field are architecturally defined except
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* bit 16 - Segment Unusable.
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*/
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struct seg_desc {
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uint64_t base;
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uint32_t limit;
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uint32_t access;
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};
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/*
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* Protections are chosen from these bits, or-ed together
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*/
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#define PROT_READ 0x01U /* pages can be read */
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#define PROT_WRITE 0x02U /* pages can be written */
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static inline uint32_t seg_desc_type(uint32_t access)
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{
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return (access & 0x001fU);
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}
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static inline bool seg_desc_present(uint32_t access)
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{
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return ((access & 0x0080U) != 0U);
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}
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static inline bool seg_desc_def32(uint32_t access)
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{
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return ((access & 0x4000U) != 0U);
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}
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static inline bool seg_desc_unusable(uint32_t access)
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{
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return ((access & 0x10000U) != 0U);
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}
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struct vm_guest_paging {
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uint64_t cr3;
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uint8_t cpl;
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enum vm_cpu_mode cpu_mode;
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enum vm_paging_mode paging_mode;
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};
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struct instr_emul_ctxt {
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struct instr_emul_vie vie;
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struct vm_guest_paging paging;
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struct acrn_vcpu *vcpu;
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};
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int32_t emulate_instruction(const struct acrn_vcpu *vcpu);
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int32_t decode_instruction(struct acrn_vcpu *vcpu);
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#endif
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@ -31,7 +31,7 @@
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#include <hypervisor.h>
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#include "instr_emul.h"
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#include <instr_emul.h>
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#include "vlapic_priv.h"
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#include "vlapic.h"
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@ -6,7 +6,7 @@
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#include <hypervisor.h>
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#include "guest/instr_emul.h"
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#include <instr_emul.h>
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static void complete_ioreq(struct acrn_vcpu *vcpu, struct io_request *io_req)
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{
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@ -0,0 +1,100 @@
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/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef INSTR_EMUL_H
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#define INSTR_EMUL_H
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struct instr_emul_vie_op {
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uint8_t op_type; /* type of operation (e.g. MOV) */
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uint16_t op_flags;
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};
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#define VIE_PREFIX_SIZE 4U
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#define VIE_INST_SIZE 15U
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struct instr_emul_vie {
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uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
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uint8_t num_valid; /* size of the instruction */
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uint8_t num_processed;
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uint8_t addrsize:4, opsize:4; /* address and operand sizes */
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uint8_t rex_w:1, /* REX prefix */
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rex_r:1,
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rex_x:1,
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rex_b:1,
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rex_present:1,
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repz_present:1, /* REP/REPE/REPZ prefix */
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repnz_present:1, /* REPNE/REPNZ prefix */
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opsize_override:1, /* Operand size override */
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addrsize_override:1, /* Address size override */
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seg_override:1; /* Segment override */
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uint8_t mod:2, /* ModRM byte */
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reg:4,
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rm:4;
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uint8_t ss:2, /* SIB byte */
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index:4,
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base:4;
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uint8_t disp_bytes;
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uint8_t imm_bytes;
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uint8_t scale;
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enum cpu_reg_name base_register; /* CPU_REG_xyz */
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enum cpu_reg_name index_register; /* CPU_REG_xyz */
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enum cpu_reg_name segment_register; /* CPU_REG_xyz */
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int64_t displacement; /* optional addr displacement */
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int64_t immediate; /* optional immediate operand */
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uint8_t decoded; /* set to 1 if successfully decoded */
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uint8_t opcode;
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struct instr_emul_vie_op op; /* opcode description */
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uint64_t dst_gpa; /* saved dst operand gpa. Only for movs */
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};
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struct vm_guest_paging {
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uint64_t cr3;
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uint8_t cpl;
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enum vm_cpu_mode cpu_mode;
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enum vm_paging_mode paging_mode;
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};
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struct instr_emul_ctxt {
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struct instr_emul_vie vie;
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struct vm_guest_paging paging;
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struct acrn_vcpu *vcpu;
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};
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int32_t emulate_instruction(const struct acrn_vcpu *vcpu);
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int32_t decode_instruction(struct acrn_vcpu *vcpu);
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#endif
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@ -16,7 +16,7 @@
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#include <gdt.h>
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#include <timer.h>
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#include <logmsg.h>
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#include "arch/x86/guest/instr_emul.h"
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#include <instr_emul.h>
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#include <profiling.h>
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#include <security.h>
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