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HV: move e820 entry out of vm description 

move e820_default_entries[] from vm_description.c to ve820.c and rename
to ve820_entry[] as a temparary solution for partiton mode e820 management;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Victor Sun 2019-01-31 13:35:51 +08:00 committed by Eddie Dong
parent ce19dd423e
commit 11bfe3d43e
7 changed files with 85 additions and 68 deletions
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1
hypervisor/Makefile
View File

@ -145,6 +145,7 @@ ifeq ($(CONFIG_SHARING_MODE),y)
C_SRCS += arch/x86/configs/sharing_config.c
else ifeq ($(CONFIG_PARTITION_MODE),y)
C_SRCS += arch/x86/configs/partition_config.c
C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/ve820.c
endif
C_SRCS += boot/acpi.c

40
hypervisor/arch/x86/configs/apl-mrb/ve820.c Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <hypervisor.h>
#include <e820.h>
const struct e820_entry ve820_entry[NUM_E820_ENTRIES] = {
{ /* 0 to mptable */
.baseaddr = 0x0U,
.length = 0xEFFFFU,
.type = E820_TYPE_RAM
},
{ /* mptable 65536U */
.baseaddr = 0xF0000U,
.length = 0x10000U,
.type = E820_TYPE_RESERVED
},
{ /* mptable to lowmem */
.baseaddr = 0x100000U,
.length = 0x1FF00000U,
.type = E820_TYPE_RAM
},
{ /* lowmem to PCI hole */
.baseaddr = 0x20000000U,
.length = 0xa0000000U,
.type = E820_TYPE_RESERVED
},
{ /* PCI hole to 4G */
.baseaddr = 0xe0000000U,
.length = 0x20000000U,
.type = E820_TYPE_RESERVED
},
};

40
hypervisor/arch/x86/configs/dnv-cb2/ve820.c Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <hypervisor.h>
#include <e820.h>
const struct e820_entry ve820_entry[NUM_E820_ENTRIES] = {
{ /* 0 to mptable */
.baseaddr = 0x0U,
.length = 0xEFFFFU,
.type = E820_TYPE_RAM
},
{ /* mptable 65536U */
.baseaddr = 0xF0000U,
.length = 0x10000U,
.type = E820_TYPE_RESERVED
},
{ /* mptable to lowmem */
.baseaddr = 0x100000U,
.length = 0x7FF00000U,
.type = E820_TYPE_RAM
},
{ /* lowmem to PCI hole */
.baseaddr = 0x80000000U,
.length = 0x40000000U,
.type = E820_TYPE_RESERVED
},
{ /* PCI hole to 4G */
.baseaddr = 0xe0000000U,
.length = 0x20000000U,
.type = E820_TYPE_RESERVED
},
};

6
hypervisor/arch/x86/e820.c
View File

@ -232,9 +232,9 @@ uint32_t create_e820_table(struct e820_entry *param_e820)
uint32_t i;
for (i = 0U; i < NUM_E820_ENTRIES; i++) {
param_e820[i].baseaddr = e820_default_entries[i].baseaddr;
param_e820[i].length = e820_default_entries[i].length;
param_e820[i].type = e820_default_entries[i].type;
param_e820[i].baseaddr = ve820_entry[i].baseaddr;
param_e820[i].length = ve820_entry[i].length;
param_e820[i].type = ve820_entry[i].type;
}
return NUM_E820_ENTRIES;

2
hypervisor/include/arch/x86/e820.h
View File

@ -62,7 +62,7 @@ const struct e820_mem_params *get_e820_mem_info(void);
* there is reserved memory of 64K for MPtable and PCI hole of 512MB
*/
#define NUM_E820_ENTRIES 5U
extern const struct e820_entry e820_default_entries[NUM_E820_ENTRIES];
extern const struct e820_entry ve820_entry[NUM_E820_ENTRIES];
#endif
#endif

32
hypervisor/partition/apl-mrb/vm_description.c
View File

@ -186,35 +186,3 @@ const struct pcpu_vm_config_mapping pcpu_vm_config_map[] = {
.is_bsp = true,
},
};
const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
{ /* 0 to mptable */
.baseaddr = 0x0U,
.length = 0xEFFFFU,
.type = E820_TYPE_RAM
},
{ /* mptable 65536U */
.baseaddr = 0xF0000U,
.length = 0x10000U,
.type = E820_TYPE_RESERVED
},
{ /* mptable to lowmem */
.baseaddr = 0x100000U,
.length = 0x1FF00000U,
.type = E820_TYPE_RAM
},
{ /* lowmem to PCI hole */
.baseaddr = 0x20000000U,
.length = 0xa0000000U,
.type = E820_TYPE_RESERVED
},
{ /* PCI hole to 4G */
.baseaddr = 0xe0000000U,
.length = 0x20000000U,
.type = E820_TYPE_RESERVED
},
};

32
hypervisor/partition/dnv-cb2/vm_description.c
View File

@ -236,35 +236,3 @@ const struct pcpu_vm_config_mapping pcpu_vm_config_map[] = {
.is_bsp = true,
},
};
const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
{ /* 0 to mptable */
.baseaddr = 0x0U,
.length = 0xEFFFFU,
.type = E820_TYPE_RAM
},
{ /* mptable 65536U */
.baseaddr = 0xF0000U,
.length = 0x10000U,
.type = E820_TYPE_RESERVED
},
{ /* mptable to lowmem */
.baseaddr = 0x100000U,
.length = 0x7FF00000U,
.type = E820_TYPE_RAM
},
{ /* lowmem to PCI hole */
.baseaddr = 0x80000000U,
.length = 0x40000000U,
.type = E820_TYPE_RESERVED
},
{ /* PCI hole to 4G */
.baseaddr = 0xe0000000U,
.length = 0x20000000U,
.type = E820_TYPE_RESERVED
},
};