hv: fix integer violations
The operands to shift operations (<<, >>) shall be unsigned integers. Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -30,12 +30,12 @@ static uint64_t x86_arch_capabilities;
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/* TODO: add more capability per requirement */
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/* TODO: add more capability per requirement */
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/* APICv features */
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/* APICv features */
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#define VAPIC_FEATURE_VIRT_ACCESS (1U << 0)
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#define VAPIC_FEATURE_VIRT_ACCESS (1U << 0U)
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#define VAPIC_FEATURE_VIRT_REG (1U << 1)
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#define VAPIC_FEATURE_VIRT_REG (1U << 1U)
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#define VAPIC_FEATURE_INTR_DELIVERY (1U << 2)
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#define VAPIC_FEATURE_INTR_DELIVERY (1U << 2U)
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#define VAPIC_FEATURE_TPR_SHADOW (1U << 3)
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#define VAPIC_FEATURE_TPR_SHADOW (1U << 3U)
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#define VAPIC_FEATURE_POST_INTR (1U << 4)
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#define VAPIC_FEATURE_POST_INTR (1U << 4U)
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#define VAPIC_FEATURE_VX2APIC_MODE (1U << 5)
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#define VAPIC_FEATURE_VX2APIC_MODE (1U << 5U)
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struct cpu_capability {
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struct cpu_capability {
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uint8_t apicv_features;
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uint8_t apicv_features;
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@ -1077,7 +1077,7 @@ remove_iommu_device(const struct iommu_domain *domain, uint16_t segment,
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context_table_addr = dmar_get_bitslice(root_entry->lower,
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context_table_addr = dmar_get_bitslice(root_entry->lower,
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ROOT_ENTRY_LOWER_CTP_MASK,
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ROOT_ENTRY_LOWER_CTP_MASK,
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ROOT_ENTRY_LOWER_CTP_POS);
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ROOT_ENTRY_LOWER_CTP_POS);
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context_table_addr = context_table_addr << 12;
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context_table_addr = context_table_addr << CPU_PAGE_SHIFT;
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context_table =
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context_table =
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(struct dmar_context_entry *)hpa2hva(context_table_addr);
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(struct dmar_context_entry *)hpa2hva(context_table_addr);
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@ -145,12 +145,12 @@ static uint8_t get_secondary_bus(uint8_t bus, uint8_t dev, uint8_t func)
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{
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{
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uint32_t data;
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uint32_t data;
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pio_write32(PCI_CFG_ENABLE | (bus << 16) | (dev << 11) |
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pio_write32(PCI_CFG_ENABLE | (bus << 16U) | (dev << 11U) |
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(func << 8) | 0x18, PCI_CONFIG_ADDR);
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(func << 8U) | 0x18U, PCI_CONFIG_ADDR);
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data = pio_read32(PCI_CONFIG_DATA);
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data = pio_read32(PCI_CONFIG_DATA);
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return (data >> 8) & 0xff;
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return (data >> 8U) & 0xffU;
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}
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}
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static uint16_t
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static uint16_t
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@ -173,7 +173,7 @@ dmar_path_bdf(int path_len, int busno,
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dev = path[i].device;
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dev = path[i].device;
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fun = path[i].function;
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fun = path[i].function;
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}
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}
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return (bus << 8 | DEVFUN(dev, fun));
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return (bus << 8U | DEVFUN(dev, fun));
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}
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}
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@ -267,8 +267,8 @@ handle_one_drhd(struct acpi_dmar_hardware_unit *acpi_drhd,
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consumed = handle_dmar_devscope(dev_scope, cp, remaining);
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consumed = handle_dmar_devscope(dev_scope, cp, remaining);
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if (((drhd->segment << 16) |
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if (((drhd->segment << 16U) |
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(dev_scope->bus << 8) |
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(dev_scope->bus << 8U) |
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dev_scope->devfun) == CONFIG_GPU_SBDF) {
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dev_scope->devfun) == CONFIG_GPU_SBDF) {
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ASSERT(dev_count == 1, "no dedicated iommu for gpu");
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ASSERT(dev_count == 1, "no dedicated iommu for gpu");
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drhd->ignore = true;
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drhd->ignore = true;
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@ -63,7 +63,7 @@
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uint32_t msrl, msrh; \
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uint32_t msrl, msrh; \
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asm volatile ("rdmsr" : "=a"(msrl), \
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asm volatile ("rdmsr" : "=a"(msrl), \
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"=d"(msrh) : "c" (reg)); \
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"=d"(msrh) : "c" (reg)); \
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*msr_val_ptr = ((uint64_t)msrh<<32) | msrl; \
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*msr_val_ptr = ((uint64_t)msrh << 32U) | msrl; \
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}
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}
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EFI_STATUS get_pe_section(CHAR8 *base, char *section, UINTN *vaddr, UINTN *size);
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EFI_STATUS get_pe_section(CHAR8 *base, char *section, UINTN *vaddr, UINTN *size);
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@ -45,8 +45,8 @@
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#define EFILINUX_VERSION_MAJOR 1
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#define EFILINUX_VERSION_MAJOR 1
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#define EFILINUX_VERSION_MINOR 0
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#define EFILINUX_VERSION_MINOR 0
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#define MEM_ADDR_1MB (1 << 20)
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#define MEM_ADDR_1MB (1U << 20U)
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#define MEM_ADDR_4GB (0xFFFFFFFF)
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#define MEM_ADDR_4GB (0xFFFFFFFFU)
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extern EFI_SYSTEM_TABLE *sys_table;
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extern EFI_SYSTEM_TABLE *sys_table;
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@ -10,7 +10,7 @@
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#include <spinlock.h>
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#include <spinlock.h>
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#define SHELL_CMD_MAX_LEN 100U
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#define SHELL_CMD_MAX_LEN 100U
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#define SHELL_STRING_MAX_LEN (CPU_PAGE_SIZE << 2)
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#define SHELL_STRING_MAX_LEN (CPU_PAGE_SIZE << 2U)
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/* Shell Command Function */
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/* Shell Command Function */
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typedef int (*shell_cmd_fn_t)(int argc, char **argv);
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typedef int (*shell_cmd_fn_t)(int argc, char **argv);
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@ -52,12 +52,12 @@
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/*enable/disable receive data read request interrupt*/
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/*enable/disable receive data read request interrupt*/
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/* definition for LCR */
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/* definition for LCR */
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#define LCR_DLAB (1U << 7) /*DLAB THR/RBR&IER or DLL&DLM= Bit 7*/
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#define LCR_DLAB (1U << 7U) /*DLAB THR/RBR&IER or DLL&DLM= Bit 7*/
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#define LCR_SB (1U << 6) /*break control on/off= Bit 6*/
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#define LCR_SB (1U << 6U) /*break control on/off= Bit 6*/
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#define LCR_SP (1U << 5) /*Specifies the operation of parity bit*/
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#define LCR_SP (1U << 5U) /*Specifies the operation of parity bit*/
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#define LCR_EPS (1U << 4) /*Specifies the logic of a parity bit*/
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#define LCR_EPS (1U << 4U) /*Specifies the logic of a parity bit*/
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#define LCR_PEN (1U << 3) /*Specifies whether to add a parity bit*/
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#define LCR_PEN (1U << 3U) /*Specifies whether to add a parity bit*/
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#define LCR_STB (1U << 2) /*stop bit length*/
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#define LCR_STB (1U << 2U) /*stop bit length*/
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#define LCR_WL8 (0x03U) /*number of bits of serial data*/
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#define LCR_WL8 (0x03U) /*number of bits of serial data*/
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#define LCR_WL7 (0x02U) /*number of bits of serial data*/
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#define LCR_WL7 (0x02U) /*number of bits of serial data*/
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#define LCR_WL6 (0x01U) /*number of bits of serial data*/
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#define LCR_WL6 (0x01U) /*number of bits of serial data*/
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@ -70,32 +70,32 @@
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/* bit definitions for LSR */
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/* bit definitions for LSR */
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/* at least one error in data within fifo */
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/* at least one error in data within fifo */
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#define LSR_ERR (1U << 7)
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#define LSR_ERR (1U << 7U)
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/* Transmit data Present */
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/* Transmit data Present */
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#define LSR_TEMT (1U << 6)
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#define LSR_TEMT (1U << 6U)
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/* Transmit data write request present */
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/* Transmit data write request present */
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#define LSR_THRE (1U << 5)
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#define LSR_THRE (1U << 5U)
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/* Break interrupt data Present */
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/* Break interrupt data Present */
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#define LSR_BI (1U << 4)
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#define LSR_BI (1U << 4U)
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/* Framing Error Occurred */
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/* Framing Error Occurred */
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#define LSR_FE (1U << 3)
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#define LSR_FE (1U << 3U)
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/* Parity Error Occurred */
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/* Parity Error Occurred */
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#define LSR_PE (1U << 2)
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#define LSR_PE (1U << 2U)
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/* Overrun error */
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/* Overrun error */
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#define LSR_OE (1U << 1)
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#define LSR_OE (1U << 1U)
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/* Readable received data is present */
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/* Readable received data is present */
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#define LSR_DR (1U << 0)
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#define LSR_DR (1U << 0U)
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/* definition for MCR */
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/* definition for MCR */
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#define MCR_RTS (1U << 1) /* Request to Send */
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#define MCR_RTS (1U << 1U) /* Request to Send */
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#define MCR_DTR (1U << 0) /* Data Terminal Ready */
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#define MCR_DTR (1U << 0U) /* Data Terminal Ready */
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/* definition for FCR */
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/* definition for FCR */
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#define FCR_RX_MASK 0xc0U
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#define FCR_RX_MASK 0xc0U
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#define FCR_DMA (1U << 3)
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#define FCR_DMA (1U << 3U)
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#define FCR_TFR (1U << 2) /* Reset Transmit Fifo */
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#define FCR_TFR (1U << 2U) /* Reset Transmit Fifo */
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#define FCR_RFR (1U << 1) /* Reset Receive Fifo */
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#define FCR_RFR (1U << 1U) /* Reset Receive Fifo */
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#define FCR_FIFOE (1U << 0) /* Fifo Enable */
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#define FCR_FIFOE (1U << 0U) /* Fifo Enable */
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#define UART_IER_DISABLE_ALL 0x00000000U
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#define UART_IER_DISABLE_ALL 0x00000000U
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@ -47,7 +47,7 @@
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#endif
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#endif
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/* Generic VM flags from guest OS */
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/* Generic VM flags from guest OS */
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#define SECURE_WORLD_ENABLED (1UL<<0U) /* Whether secure world is enabled */
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#define SECURE_WORLD_ENABLED (1UL << 0U) /* Whether secure world is enabled */
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/**
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/**
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* @brief Hypercall
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* @brief Hypercall
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