hv: cpu: refine secondary cpu start up
1) add a write memory barrier after setting pcpu_sync to one to let this change visible to AP immediately. 2) there's only BSP will set pcpu_sync, so there's no memory order issue between CPUs. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -5,7 +5,6 @@
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*/
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#include <types.h>
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#include <atomic.h>
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#include <bits.h>
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#include <page.h>
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#include <e820.h>
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@ -311,7 +310,8 @@ bool start_pcpus(uint64_t mask)
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uint64_t expected_start_mask = mask;
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/* secondary cpu start up will wait for pcpu_sync -> 0UL */
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atomic_store64(&pcpu_sync, 1UL);
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pcpu_sync = 1UL;
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cpu_write_memory_barrier();
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i = ffs64(expected_start_mask);
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while (i != INVALID_BIT_INDEX) {
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@ -326,7 +326,7 @@ bool start_pcpus(uint64_t mask)
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}
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/* Trigger event to allow secondary CPUs to continue */
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atomic_store64(&pcpu_sync, 0UL);
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pcpu_sync = 0UL;
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return ((pcpu_active_bitmap & mask) == mask);
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}
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