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acrn-hypervisor/misc/acrn-config/xmls/board-xmls/nuc7i7dnb.xml

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acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
<acrn-config board="nuc7i7dnb">
<BIOS_INFO>
BIOS Information
Vendor: Intel Corp.
Version: DNKBLi7v.86A.0065.2019.0611.1424
Release Date: 06/11/2019
BIOS Revision: 5.6
</BIOS_INFO>
<BASE_BOARD_INFO>
Base Board Information
Manufacturer: Intel Corporation
Product Name: NUC7i7DNB
Version: J83500-204
</BASE_BOARD_INFO>
<PCI_DEVICE>
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers (rev 08)
00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 07)
Region 0: Memory at de000000 (64-bit, non-prefetchable) [size=16M]
Region 2: Memory at c0000000 (64-bit, prefetchable) [size=256M]
00:08.0 System peripheral: Intel Corporation Skylake Gaussian Mixture Model
Region 0: Memory at df252000 (64-bit, non-prefetchable) [disabled] [size=4K]
00:14.0 USB controller: Intel Corporation Sunrise Point-LP USB 3.0 xHCI Controller (rev 21)
Region 0: Memory at df230000 (64-bit, non-prefetchable) [size=64K]
00:14.2 Signal processing controller: Intel Corporation Sunrise Point-LP Thermal subsystem (rev 21)
Region 0: Memory at df251000 (64-bit, non-prefetchable) [size=4K]
00:15.0 Signal processing controller: Intel Corporation Sunrise Point-LP Serial IO I2C Controller #0 (rev 21)
Region 0: Memory at df250000 (64-bit, non-prefetchable) [size=4K]
00:15.1 Signal processing controller: Intel Corporation Sunrise Point-LP Serial IO I2C Controller #1 (rev 21)
Region 0: Memory at df24f000 (64-bit, non-prefetchable) [size=4K]
00:16.0 Communication controller: Intel Corporation Sunrise Point-LP CSME HECI #1 (rev 21)
Region 0: Memory at df24e000 (64-bit, non-prefetchable) [size=4K]
00:16.3 Serial controller: Intel Corporation Device 9d3d (rev 21)
Region 1: Memory at df24d000 (32-bit, non-prefetchable) [size=4K]
00:17.0 SATA controller: Intel Corporation Sunrise Point-LP SATA Controller [AHCI mode] (rev 21)
Region 0: Memory at df248000 (32-bit, non-prefetchable) [size=8K]
Region 1: Memory at df24c000 (32-bit, non-prefetchable) [size=256]
Region 5: Memory at df24b000 (32-bit, non-prefetchable) [size=2K]
00:1c.0 PCI bridge: Intel Corporation Sunrise Point-LP PCI Express Root Port (rev f1)
00:1d.0 PCI bridge: Intel Corporation Sunrise Point-LP PCI Express Root Port #9 (rev f1)
00:1f.0 ISA bridge: Intel Corporation Device 9d4e (rev 21)
00:1f.2 Memory controller: Intel Corporation Sunrise Point-LP PMC (rev 21)
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
Region 0: Memory at df244000 (32-bit, non-prefetchable) [disabled] [size=16K]
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
00:1f.3 Audio device: Intel Corporation Sunrise Point-LP HD Audio (rev 21)
Region 0: Memory at df240000 (64-bit, non-prefetchable) [size=16K]
Region 4: Memory at df220000 (64-bit, non-prefetchable) [size=64K]
00:1f.4 SMBus: Intel Corporation Sunrise Point-LP SMBus (rev 21)
Region 0: Memory at df24a000 (64-bit, non-prefetchable) [size=256]
00:1f.6 Ethernet controller: Intel Corporation Ethernet Connection I219-LM (rev 21)
Region 0: Memory at df200000 (32-bit, non-prefetchable) [size=128K]
01:00.0 Network controller: Intel Corporation Wireless 8265 / 8275 (rev 78)
Region 0: Memory at df100000 (64-bit, non-prefetchable) [size=8K]
02:00.0 Non-Volatile memory controller: Intel Corporation Device f1a6 (rev 03)
Region 0: Memory at df000000 (64-bit, non-prefetchable) [size=16K]
</PCI_DEVICE>
<PCI_VID_PID>
00:00.0 0600: 8086:5914 (rev 08)
00:02.0 0300: 8086:5917 (rev 07)
00:08.0 0880: 8086:1911
00:14.0 0c03: 8086:9d2f (rev 21)
00:14.2 1180: 8086:9d31 (rev 21)
00:15.0 1180: 8086:9d60 (rev 21)
00:15.1 1180: 8086:9d61 (rev 21)
00:16.0 0780: 8086:9d3a (rev 21)
00:16.3 0700: 8086:9d3d (rev 21)
00:17.0 0106: 8086:9d03 (rev 21)
00:1c.0 0604: 8086:9d12 (rev f1)
00:1d.0 0604: 8086:9d18 (rev f1)
00:1f.0 0601: 8086:9d4e (rev 21)
00:1f.2 0580: 8086:9d21 (rev 21)
00:1f.3 0403: 8086:9d71 (rev 21)
00:1f.4 0c05: 8086:9d23 (rev 21)
00:1f.6 0200: 8086:156f (rev 21)
01:00.0 0280: 8086:24fd (rev 78)
02:00.0 0108: 8086:f1a6 (rev 03)
</PCI_VID_PID>
<WAKE_VECTOR_INFO>
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
#define WAKE_VECTOR_32 0x8AA09F8CUL
#define WAKE_VECTOR_64 0x8AA09F98UL
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
</WAKE_VECTOR_INFO>
<RESET_REGISTER_INFO>
#define RESET_REGISTER_ADDRESS 0xCF9UL
#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
#define RESET_REGISTER_VALUE 0x6U
</RESET_REGISTER_INFO>
<PM_INFO>
#define PM1A_EVT_SPACE_ID SPACE_SYSTEM_IO
#define PM1A_EVT_BIT_WIDTH 0x20U
#define PM1A_EVT_BIT_OFFSET 0x0U
#define PM1A_EVT_ADDRESS 0x1800UL
#define PM1A_EVT_ACCESS_SIZE 0x2U
#define PM1B_EVT_SPACE_ID SPACE_SYSTEM_IO
#define PM1B_EVT_BIT_WIDTH 0x0U
#define PM1B_EVT_BIT_OFFSET 0x0U
#define PM1B_EVT_ADDRESS 0x0UL
#define PM1B_EVT_ACCESS_SIZE 0x2U
#define PM1A_CNT_SPACE_ID SPACE_SYSTEM_IO
#define PM1A_CNT_BIT_WIDTH 0x10U
#define PM1A_CNT_BIT_OFFSET 0x0U
#define PM1A_CNT_ADDRESS 0x1804UL
#define PM1A_CNT_ACCESS_SIZE 0x2U
#define PM1B_CNT_SPACE_ID SPACE_SYSTEM_IO
#define PM1B_CNT_BIT_WIDTH 0x0U
#define PM1B_CNT_BIT_OFFSET 0x0U
#define PM1B_CNT_ADDRESS 0x0UL
#define PM1B_CNT_ACCESS_SIZE 0x2U
</PM_INFO>
<S3_INFO>
#define S3_PKG_VAL_PM1A 0x5U
#define S3_PKG_VAL_PM1B 0U
#define S3_PKG_RESERVED 0x0U
</S3_INFO>
<S5_INFO>
#define S5_PKG_VAL_PM1A 0x7U
#define S5_PKG_VAL_PM1B 0U
#define S5_PKG_RESERVED 0x0U
</S5_INFO>
<DRHD_INFO>
#define DRHD_COUNT 2U
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
#define DRHD0_DEV_CNT 0x1U
#define DRHD0_SEGMENT 0x0U
#define DRHD0_FLAGS 0x0U
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
#define DRHD0_REG_BASE 0xFED90000UL
acrn-config: correct value of DRHDx_IGNORE macro The DRHDx_IGNORE should be defined to true when DRHD device BDF equal to the given CONFIG_GPU_SBDF. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 09:33:39 +08:00
#define DRHD0_IGNORE true
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
#define DRHD0_DEVSCOPE0_TYPE 0x1U
#define DRHD0_DEVSCOPE0_ID 0x0U
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
#define DRHD0_DEVSCOPE0_BUS 0x0U
#define DRHD0_DEVSCOPE0_PATH 0x10U
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
#define DRHD1_DEV_CNT 0x2U
#define DRHD1_SEGMENT 0x0U
#define DRHD1_FLAGS 0x1U
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
#define DRHD1_REG_BASE 0xFED91000UL
#define DRHD1_IGNORE false
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
#define DRHD1_DEVSCOPE0_TYPE 0x3U
#define DRHD1_DEVSCOPE0_ID 0x2U
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
#define DRHD1_DEVSCOPE0_BUS 0xf0U
#define DRHD1_DEVSCOPE0_PATH 0xf8U
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
#define DRHD1_DEVSCOPE1_TYPE 0x4U
#define DRHD1_DEVSCOPE1_ID 0x0U
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
#define DRHD1_DEVSCOPE1_BUS 0x0U
#define DRHD1_DEVSCOPE1_PATH 0xf8U
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
</DRHD_INFO>
<CPU_BRAND>
"Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz"
</CPU_BRAND>
<CX_INFO>
{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0x97U, 0x00U}, /* C2 */
{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */
</CX_INFO>
<PX_INFO>
{0x835UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002A00UL, 0x002A00UL}, /* P0 */
{0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL}, /* P1 */
{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P2 */
{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P3 */
{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P4 */
{0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P5 */
{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P6 */
{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P7 */
{0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL}, /* P8 */
{0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P9 */
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P10 */
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P11 */
{0x2BCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000700UL, 0x000700UL}, /* P12 */
{0x258UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000600UL, 0x000600UL}, /* P13 */
{0x1F4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000500UL, 0x000500UL}, /* P14 */
{0x190UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000400UL, 0x000400UL}, /* P15 */
</PX_INFO>
acrn-config: add MMCFG_BASE_INFO item in board config Parse MMCFG base address value and store it to board config xml as DEFAULT_PCI_MMCFG_BASE macro. Tracked-On: #4173 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-12-02 10:04:37 +08:00
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
<CLOS_INFO>
clos supported by cache:False
clos max:0
</CLOS_INFO>
<SYSTEM_RAM_INFO>
00001000-00057fff : System RAM
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
00059000-0009dfff : System RAM
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
00100000-3fffffff : System RAM
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
40400000-7da93fff : System RAM
7da96000-8a0dafff : System RAM
8afff000-8affffff : System RAM
100000000-26dffffff : System RAM
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
</SYSTEM_RAM_INFO>
acrn-config: modify rootfs tag in board information 1. grap 'ext4' rootfs, and store it as "BLOCK_DEVICE_INFO" tag 2. remove 'Tab' from app tools 3. add support to parse ' ' from scenario xml v1-v2: 1). modify the board info "ROOT_DEVICE_INFO" -> "BLOCK_DEVICE_INFO" Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-18 09:09:24 +08:00
<BLOCK_DEVICE_INFO>
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
/dev/sda3: TYPE="ext4"
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
/dev/nvme0n1p3: TYPE="ext4"
/dev/nvme0n1p4: TYPE="ext4"
acrn-config: modify rootfs tag in board information 1. grap 'ext4' rootfs, and store it as "BLOCK_DEVICE_INFO" tag 2. remove 'Tab' from app tools 3. add support to parse ' ' from scenario xml v1-v2: 1). modify the board info "ROOT_DEVICE_INFO" -> "BLOCK_DEVICE_INFO" Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-18 09:09:24 +08:00
</BLOCK_DEVICE_INFO>
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
<TTYS_INFO>
acrn-config: refine ttyS info of board file The previous method to handle ttyS info has an assumption that PCI serial devices are all mmio type, this caused incorrect BDF info in board XML file. This patch fix this issue by dropping serial device BDF info and replace it with IO type. Tracked-On: #3900 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-10-23 11:27:12 +08:00
seri:/dev/ttyS0 type:portio base:0x3F8 irq:4
seri:/dev/ttyS4 type:portio base:0xF0A0 irq:19
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
</TTYS_INFO>
<AVAILABLE_IRQ_INFO>
3, 5, 6, 7, 10, 11, 12, 13, 15
</AVAILABLE_IRQ_INFO>
<TOTAL_MEM_INFO>
acrn-config: update DRHD_INFO section for board xml The DRHD_INFO section should be updated with the refinement patches for parsing DMAR table. Tracked-On: #3854 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
2019-11-05 10:57:23 +08:00
8033848 kB
acrn-config: add xmls for acrn-config tools 1. add $(board) xmls which generate by acrn-config/target acrn-config/target/board_parser.py will generate native board information and store to $(board).xml then, acrn-config/board_config/board_cfg_gen.py will use the xml to generate hypervisor/arch/x86/configs/$(board)/ source file and apply to the local acrn-hypervisor 2. add $(scenario) xmls for acrn-config/scenario_config to config scenario acrn-config/scenario_config/scenario_cfg_gen.py will parse scenario xmls and generate hypervisor/scenarios/$(scenario) source file and apply to the local acrn-hypervisor Tracked-On: #3602 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com> Acked-by: Terry Zou <terry.zou@intel.com>
2019-09-10 18:29:35 +08:00
</TOTAL_MEM_INFO>
<CPU_PROCESSOR_INFO>
0, 1, 2, 3
</CPU_PROCESSOR_INFO>
</acrn-config>