2018-06-14 18:06:26 +08:00
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PTDEV_H
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#define PTDEV_H
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2018-07-18 13:36:41 +08:00
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#define ACTIVE_FLAG 0x1U /* any non zero should be okay */
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2018-06-14 18:06:26 +08:00
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2018-08-20 10:47:35 +08:00
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#define PTDEV_INTR_MSI (1U << 0U)
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#define PTDEV_INTR_INTX (1U << 1U)
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2018-06-14 18:06:26 +08:00
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2018-11-19 11:19:10 +08:00
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#define INVALID_PTDEV_ENTRY_ID 0xffffU
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2018-12-19 14:36:34 +08:00
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#define PTDEV_VPIN_IOAPIC 0x0U
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#define PTDEV_VPIN_PIC 0x1U
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2018-06-14 18:06:26 +08:00
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2018-08-20 10:47:35 +08:00
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#define DEFINE_MSI_SID(name, a, b) \
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2018-09-05 10:55:29 +08:00
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union source_id (name) = {.msi_id = {.bdf = (a), .entry_nr = (b)} }
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2018-08-20 10:47:35 +08:00
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#define DEFINE_IOAPIC_SID(name, a, b) \
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2018-09-05 10:55:29 +08:00
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union source_id (name) = {.intx_id = {.pin = (a), .src = (b)} }
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2018-08-20 10:47:35 +08:00
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union source_id {
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uint32_t value;
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struct {
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uint16_t bdf;
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uint16_t entry_nr;
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} msi_id;
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struct {
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uint8_t pin;
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uint8_t src;
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uint16_t reserved;
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} intx_id;
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};
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2018-06-14 18:06:26 +08:00
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/* entry per guest virt vector */
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2018-11-29 15:26:27 +08:00
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struct ptirq_msi_info {
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2018-10-16 13:26:14 +08:00
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uint64_t vmsi_addr; /* virt msi_addr */
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2018-06-14 18:06:26 +08:00
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uint32_t vmsi_data; /* virt msi_data */
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2018-10-16 13:26:14 +08:00
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uint64_t pmsi_addr; /* phys msi_addr */
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2018-06-14 18:06:26 +08:00
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uint32_t pmsi_data; /* phys msi_data */
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2018-12-08 00:30:49 +08:00
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int32_t is_msix; /* 0-MSI, 1-MSIX */
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2018-06-14 18:06:26 +08:00
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};
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/* entry per each allocated irq/vector
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* it represents a pass-thru device's remapping data entry which collecting
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* information related with its vm and msi/intx mapping & interaction nodes
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* with interrupt handler and softirq.
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*/
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2018-11-29 15:26:27 +08:00
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struct ptirq_remapping_info {
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2018-11-19 11:19:10 +08:00
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uint16_t ptdev_entry_id;
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2018-08-20 10:47:35 +08:00
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uint32_t intr_type;
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union source_id phys_sid;
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union source_id virt_sid;
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2018-11-05 13:28:23 +08:00
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struct acrn_vm *vm;
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2018-06-14 18:06:26 +08:00
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uint32_t active; /* 1=active, 0=inactive and to free*/
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2018-08-07 14:33:02 +08:00
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uint32_t allocated_pirq;
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2018-09-28 15:20:02 +08:00
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uint32_t polarity; /* 0=active high, 1=active low*/
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2018-06-14 18:06:26 +08:00
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struct list_head softirq_node;
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2018-11-29 15:26:27 +08:00
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struct ptirq_msi_info msi;
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2018-09-13 16:31:17 +08:00
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uint64_t intr_count;
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struct hv_timer intr_delay_timer; /* used for delay intr injection */
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2018-06-14 18:06:26 +08:00
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};
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2018-12-18 22:22:10 +08:00
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extern struct ptirq_remapping_info ptirq_entries[CONFIG_MAX_PT_IRQ_ENTRIES];
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2018-06-14 18:06:26 +08:00
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extern spinlock_t ptdev_lock;
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2018-11-29 15:26:27 +08:00
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bool is_entry_active(const struct ptirq_remapping_info *entry);
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2018-11-29 16:42:45 +08:00
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void ptirq_softirq(uint16_t pcpu_id);
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2018-06-14 18:06:26 +08:00
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void ptdev_init(void);
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2018-11-05 13:28:23 +08:00
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void ptdev_release_all_entries(const struct acrn_vm *vm);
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2018-06-14 18:06:26 +08:00
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2018-11-29 16:42:45 +08:00
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struct ptirq_remapping_info *ptirq_dequeue_softirq(struct acrn_vm *vm);
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struct ptirq_remapping_info *ptirq_alloc_entry(struct acrn_vm *vm, uint32_t intr_type);
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void ptirq_release_entry(struct ptirq_remapping_info *entry);
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int32_t ptirq_activate_entry(struct ptirq_remapping_info *entry, uint32_t phys_irq);
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void ptirq_deactivate_entry(struct ptirq_remapping_info *entry);
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2018-06-14 18:06:26 +08:00
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2018-11-29 16:42:45 +08:00
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uint32_t ptirq_get_intr_data(const struct acrn_vm *target_vm, uint64_t *buffer, uint32_t buffer_cnt);
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2018-09-13 16:31:17 +08:00
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2018-06-14 18:06:26 +08:00
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#endif /* PTDEV_H */
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