2018-08-08 09:21:23 +08:00
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/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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2019-03-22 07:53:49 +08:00
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#ifndef VPCI_PRIV_H_
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#define VPCI_PRIV_H_
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2018-08-08 09:21:23 +08:00
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2018-09-20 13:47:01 +08:00
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#include <pci.h>
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2018-08-08 09:21:23 +08:00
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2018-09-25 03:29:01 +08:00
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static inline bool in_range(uint32_t value, uint32_t lower, uint32_t len)
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{
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return ((value >= lower) && (value < (lower + len)));
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}
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2018-12-15 03:55:06 +08:00
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static inline uint8_t pci_vdev_read_cfg_u8(const struct pci_vdev *vdev, uint32_t offset)
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2018-08-08 09:52:46 +08:00
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{
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2018-10-30 07:38:41 +08:00
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return vdev->cfgdata.data_8[offset];
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2018-08-08 09:52:46 +08:00
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}
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2018-12-15 03:55:06 +08:00
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static inline uint16_t pci_vdev_read_cfg_u16(const struct pci_vdev *vdev, uint32_t offset)
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2018-08-08 09:52:46 +08:00
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{
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2018-10-30 07:38:41 +08:00
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return vdev->cfgdata.data_16[offset >> 1U];
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2018-08-08 09:52:46 +08:00
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}
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2018-12-15 03:55:06 +08:00
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static inline uint32_t pci_vdev_read_cfg_u32(const struct pci_vdev *vdev, uint32_t offset)
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2018-08-08 09:52:46 +08:00
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{
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2018-10-30 07:38:41 +08:00
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return vdev->cfgdata.data_32[offset >> 2U];
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2018-08-08 09:52:46 +08:00
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}
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2018-10-30 07:38:41 +08:00
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static inline void pci_vdev_write_cfg_u8(struct pci_vdev *vdev, uint32_t offset, uint8_t val)
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2018-08-08 09:52:46 +08:00
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{
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2018-10-30 07:38:41 +08:00
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vdev->cfgdata.data_8[offset] = val;
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2018-08-08 09:52:46 +08:00
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}
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2018-10-30 07:38:41 +08:00
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static inline void pci_vdev_write_cfg_u16(struct pci_vdev *vdev, uint32_t offset, uint16_t val)
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2018-08-08 09:52:46 +08:00
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{
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2018-10-30 07:38:41 +08:00
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vdev->cfgdata.data_16[offset >> 1U] = val;
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2018-08-08 09:52:46 +08:00
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}
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2018-10-30 07:38:41 +08:00
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static inline void pci_vdev_write_cfg_u32(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
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2018-08-08 09:52:46 +08:00
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{
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2018-10-30 07:38:41 +08:00
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vdev->cfgdata.data_32[offset >> 2U] = val;
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2018-08-08 09:52:46 +08:00
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}
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2019-04-03 13:51:32 +08:00
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/**
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* @pre vdev != NULL
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*/
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static inline bool has_msix_cap(const struct pci_vdev *vdev)
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{
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return (vdev->msix.capoff != 0U);
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}
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2019-05-14 09:26:13 +08:00
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/**
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* @pre vdev != NULL
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*/
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static inline bool is_hostbridge(const struct pci_vdev *vdev)
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{
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return (vdev->vbdf.value == 0U);
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}
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2019-05-15 05:27:30 +08:00
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void init_vhostbridge(struct pci_vdev *vdev);
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2019-05-15 06:36:21 +08:00
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int32_t vhostbridge_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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2019-05-15 06:56:13 +08:00
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int32_t vhostbridge_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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2019-05-15 05:51:11 +08:00
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void deinit_vhostbridge(__unused const struct pci_vdev *vdev);
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2019-03-07 06:03:27 +08:00
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2019-05-14 09:00:26 +08:00
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void init_vdev_pt(struct pci_vdev *vdev);
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2019-05-15 06:36:21 +08:00
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int32_t vdev_pt_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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2019-05-15 06:56:13 +08:00
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int32_t vdev_pt_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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2019-03-07 06:03:27 +08:00
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2019-05-15 05:27:30 +08:00
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void init_vmsi(struct pci_vdev *vdev);
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2019-05-15 06:36:21 +08:00
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int32_t vmsi_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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2019-05-15 06:56:13 +08:00
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int32_t vmsi_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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2019-05-15 05:51:11 +08:00
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void deinit_vmsi(const struct pci_vdev *vdev);
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2019-05-15 05:27:30 +08:00
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void init_vmsix(struct pci_vdev *vdev);
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2019-04-03 13:51:32 +08:00
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void vdev_pt_remap_msix_table_bar(struct pci_vdev *vdev);
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int32_t vmsix_table_mmio_access_handler(struct io_request *io_req, void *handler_private_data);
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2019-05-15 06:36:21 +08:00
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int32_t vmsix_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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2019-05-15 06:56:13 +08:00
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int32_t vmsix_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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2019-05-15 05:51:11 +08:00
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void deinit_vmsix(const struct pci_vdev *vdev);
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2018-10-09 08:08:04 +08:00
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2018-12-15 03:55:06 +08:00
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uint32_t pci_vdev_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes);
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2018-09-25 03:12:20 +08:00
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void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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2018-08-08 09:52:46 +08:00
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2019-02-16 04:47:24 +08:00
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struct pci_vdev *pci_find_vdev_by_vbdf(const struct acrn_vpci *vpci, union pci_bdf vbdf);
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struct pci_vdev *pci_find_vdev_by_pbdf(const struct acrn_vpci *vpci, union pci_bdf pbdf);
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2019-03-22 07:53:49 +08:00
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#endif /* VPCI_PRIV_H_ */
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