2018-12-10 13:47:39 +08:00
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CPUINFO_H
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#define CPUINFO_H
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/* type of speculation control
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* 0 - no speculation control support
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* 1 - raw IBRS + IPBP support
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* 2 - with STIBP optimization support
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*/
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#define IBRS_NONE 0
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#define IBRS_RAW 1
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#define IBRS_OPT 2
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#ifndef ASSEMBLER
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extern int32_t ibrs_type;
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struct cpu_state_info {
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uint8_t px_cnt; /* count of all Px states */
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const struct cpu_px_data *px_data;
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uint8_t cx_cnt; /* count of all Cx entries */
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const struct cpu_cx_data *cx_data;
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};
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#define MAX_PSTATE 20U /* max num of supported Px count */
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#define MAX_CSTATE 8U /* max num of supported Cx count */
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/* We support MAX_CSTATE num of Cx, means have (MAX_CSTATE - 1) Cx entries,
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* i.e. supported Cx entry index range from 1 to MAX_CX_ENTRY.
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*/
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#define MAX_CX_ENTRY (MAX_CSTATE - 1U)
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/* CPUID feature words */
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#define FEAT_1_ECX 0U /* CPUID[1].ECX */
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#define FEAT_1_EDX 1U /* CPUID[1].EDX */
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#define FEAT_7_0_EBX 2U /* CPUID[EAX=7,ECX=0].EBX */
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#define FEAT_7_0_ECX 3U /* CPUID[EAX=7,ECX=0].ECX */
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#define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */
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#define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */
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#define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */
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#define FEAT_8000_0008_EBX 7U /* CPUID[8000_0008].EAX */
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#define FEATURE_WORDS 8U
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struct cpuinfo_x86 {
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uint8_t family, model;
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uint8_t virt_bits;
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uint8_t phys_bits;
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uint32_t cpuid_level;
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uint32_t extended_cpuid_level;
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uint64_t physical_address_mask;
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uint32_t cpuid_leaves[FEATURE_WORDS];
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char model_name[64];
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struct cpu_state_info state_info;
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};
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extern struct cpuinfo_x86 boot_cpu_data;
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2018-12-10 14:58:28 +08:00
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bool has_monitor_cap(void);
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2018-12-10 13:47:39 +08:00
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bool is_apicv_reg_virtualization_supported(void);
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bool is_apicv_intr_delivery_supported(void);
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bool is_apicv_posted_intr_supported(void);
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bool is_ept_supported(void);
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bool cpu_has_cap(uint32_t bit);
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bool cpu_has_vmx_ept_cap(uint32_t bit_mask);
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bool cpu_has_vmx_vpid_cap(uint32_t bit_mask);
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void get_cpu_capabilities(void);
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void get_cpu_name(void);
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void cpu_cap_detect(void);
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bool check_cpu_security_config(void);
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void cpu_l1d_flush(void);
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int hardware_detect_support(void);
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#endif /* ASSEMBLER */
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#endif /* CPUINFO_H */
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