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acrn-hypervisor/hypervisor/include/arch/x86/guest/vcpu.h

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initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
license: Replace license text with SPDX tag Replace the BSD-3-Clause boiler plate license text with an SPDX tag. Fixes: #189 Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-05-26 01:49:13 +08:00
* SPDX-License-Identifier: BSD-3-Clause
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
*/
#ifndef _VCPU_H_
#define _VCPU_H_
HV:common:fix "integer type violations" fix integer type violations,keep some violations which related to hypcall and msix_entry_index. V1->V2:1.modified API_MAJOR_VERSION from Makefile 2.sync acrn_common.h changed to device model Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-17 14:16:06 +08:00
#define ACRN_VCPU_MMIO_COMPLETE (0U)
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* Size of various elements within the VCPU structure */
#define REG_SIZE 8
/* Number of GPRs saved / restored for guest in VCPU structure */
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
#define NUM_GPRS 16U
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
#define GUEST_STATE_AREA_SIZE 512
HV:CPU:Constant values replace with CPU MACRO MISRA C requires that all unsigned constants should have the suffix 'U/UL'(e.g. 0xffU), but the assembler may not accept such C-style constants. To work this around, all unsigned constants must be explicitly spells out in assembly with a comment tracking the original expression from which the magic number is calculated. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-06 13:05:10 +08:00
#define CPU_CONTEXT_OFFSET_RAX 0U
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
#define CPU_CONTEXT_OFFSET_RCX 8U
#define CPU_CONTEXT_OFFSET_RDX 16U
#define CPU_CONTEXT_OFFSET_RBX 24U
#define CPU_CONTEXT_OFFSET_RSP 32U
#define CPU_CONTEXT_OFFSET_RBP 40U
#define CPU_CONTEXT_OFFSET_RSI 48U
#define CPU_CONTEXT_OFFSET_RDI 56U
#define CPU_CONTEXT_OFFSET_R8 64U
#define CPU_CONTEXT_OFFSET_R9 72U
#define CPU_CONTEXT_OFFSET_R10 80U
#define CPU_CONTEXT_OFFSET_R11 88U
#define CPU_CONTEXT_OFFSET_R12 96U
#define CPU_CONTEXT_OFFSET_R13 104U
#define CPU_CONTEXT_OFFSET_R14 112U
#define CPU_CONTEXT_OFFSET_R15 120U
#define CPU_CONTEXT_OFFSET_CR0 128U
#define CPU_CONTEXT_OFFSET_CR2 136U
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
#define CPU_CONTEXT_OFFSET_CR4 144U
#define CPU_CONTEXT_OFFSET_RIP 152U
#define CPU_CONTEXT_OFFSET_RFLAGS 160U
#define CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL 168U
#define CPU_CONTEXT_OFFSET_IA32_EFER 176U
#define CPU_CONTEXT_OFFSET_EXTCTX_START 184U
#define CPU_CONTEXT_OFFSET_CR3 184U
#define CPU_CONTEXT_OFFSET_IDTR 192U
#define CPU_CONTEXT_OFFSET_LDTR 216U
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/*sizes of various registers within the VCPU data structure */
#define VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE GUEST_STATE_AREA_SIZE
#ifndef ASSEMBLER
HV: vlapic: minimize explicit casts by adjusting types To minimize explicit casts, this patch adjusts the types of function parameters and structure fields related to vlapic and update the types in the internal implementation accordingly. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 17:11:27 +08:00
#include <guest.h>
hv: move define of struct cpu_gp_regs to a separate headfile EFI stub code need to reference to the struct cpu_gp_regs, which is currently defined in vcpu.h, however include vcpu.h in EFI stub code will include other header files not requried by EFI stub code. After moving the define of struct cpu_gp_regs to a separate headfile, the file can be included in EFI stub code without other header files. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-28 22:08:29 +08:00
#include <gpr.h>
HV: vlapic: minimize explicit casts by adjusting types To minimize explicit casts, this patch adjusts the types of function parameters and structure fields related to vlapic and update the types in the internal implementation accordingly. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 17:11:27 +08:00
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
enum vcpu_state {
VCPU_INIT,
VCPU_RUNNING,
VCPU_PAUSED,
VCPU_ZOMBIE,
VCPU_UNKNOWN_STATE,
};
HV: handle integral issue report by MISRA-C The main focus on: constant suffix U/UL; parameters cast like uint32 to a uint16 variable; unify some APIs interface, consist with the callers. also modify some places to unify code style Signed-off-by: Minggui Cao <minggui.cao@intel.com>
2018-07-12 11:47:49 +08:00
enum vm_cpu_mode {
CPU_MODE_REAL,
CPU_MODE_PROTECTED,
CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
};
HV:treewide:rename union lapic_id and struct segment For data structure types "union lapic_id and struct segment", its name is identical with variable name in the same scope. This MISRA C violation is detected by static analysis tool. Naming convention rule:If the data structure is corresponding to hardware resource (such as register, segment selector), its name need resource shorten name suffix (such as _reg, _sel). The following udpates are made: union lapic_id-->union lapic_id_reg struct segment-->struct segment_sel Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-27 16:20:58 +08:00
struct segment_sel {
HV:treewide:Add exec_vmread32 and exec_vmwrite32 functions In the hypervisor, VMCS fields include 16-bit fields, 32-bit fields, 64-bit fields and natural-width fields. In the current implement, no exec_vmread32/exec_vmwrite32 is for accessing 32-bit fields. So there are many type casting for the return value and parameters vmread/vmwrite operations. Create exec_vmread32 and exec_vmwrite32 functions to access 32-bit fields in VMCS; Update related variables type for vmread/vmwrite operations; Update related caller according to VMCS fields size. V1--V2: This is new part of this patch serial to only update 32 bit vmread/vmread opertions and related caller. V2-->V3: Update related variables type in data structure for exec_vmread32/exec_vmwrite32. Rename temp variable 'low' into 'value' for exec_vmread32; V3-->V4: Remove useless type conversion. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-16 15:43:25 +08:00
uint16_t selector;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
uint64_t base;
HV:treewide:Add exec_vmread32 and exec_vmwrite32 functions In the hypervisor, VMCS fields include 16-bit fields, 32-bit fields, 64-bit fields and natural-width fields. In the current implement, no exec_vmread32/exec_vmwrite32 is for accessing 32-bit fields. So there are many type casting for the return value and parameters vmread/vmwrite operations. Create exec_vmread32 and exec_vmwrite32 functions to access 32-bit fields in VMCS; Update related variables type for vmread/vmwrite operations; Update related caller according to VMCS fields size. V1--V2: This is new part of this patch serial to only update 32 bit vmread/vmread opertions and related caller. V2-->V3: Update related variables type in data structure for exec_vmread32/exec_vmwrite32. Rename temp variable 'low' into 'value' for exec_vmread32; V3-->V4: Remove useless type conversion. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-16 15:43:25 +08:00
uint32_t limit;
uint32_t attr;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
};
struct run_context {
/* Contains the guest register set.
* NOTE: This must be the first element in the structure, so that the offsets
* in vmx_asm.S match
*/
union {
hv: cpu: align general-purpose register layout with vmx In current code, general-purpose register layout in run_context is not align with the general-purpose register index when vmexit. So hv needs to map the index used during vmexit to the index of the general-purpose register in run_context. This patch align the layout, so that no mapping needed. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 18:50:37 +08:00
struct cpu_gp_regs regs;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
uint64_t longs[NUM_GPRS];
} guest_cpu_regs;
/** The guests CR registers 0, 2, 3 and 4. */
uint64_t cr0;
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
/* CPU_CONTEXT_OFFSET_CR2 =
* offsetof(struct run_context, cr2) = 136
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
*/
uint64_t cr2;
uint64_t cr4;
uint64_t rip;
uint64_t rflags;
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
/* CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL =
* offsetof(struct run_context, ia32_spec_ctrl) = 168
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
*/
uint64_t ia32_spec_ctrl;
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
uint64_t ia32_efer;
};
/*
* extended context does not save/restore during vm exity/entry, it's mainly
* used in trusty world switch
*/
struct ext_context {
uint64_t cr3;
/* segment registers */
struct segment_sel idtr;
struct segment_sel ldtr;
struct segment_sel gdtr;
struct segment_sel tr;
struct segment_sel cs;
struct segment_sel ss;
struct segment_sel ds;
struct segment_sel es;
struct segment_sel fs;
struct segment_sel gs;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
uint64_t ia32_star;
uint64_t ia32_lstar;
uint64_t ia32_fmask;
uint64_t ia32_kernel_gs_base;
uint64_t ia32_pat;
hv: add context->vmx_ia32_pat to save and restore VMCS Similar to cr0/4: - use context->vmx_ia32_pat to save/restore VMX_GUEST_IA32_PAT field - use context->ia32_pat to keep track the guest' view of IA32_PAT MSR Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-22 07:51:21 +08:00
uint64_t vmx_ia32_pat;
HV:treewide:Add exec_vmread32 and exec_vmwrite32 functions In the hypervisor, VMCS fields include 16-bit fields, 32-bit fields, 64-bit fields and natural-width fields. In the current implement, no exec_vmread32/exec_vmwrite32 is for accessing 32-bit fields. So there are many type casting for the return value and parameters vmread/vmwrite operations. Create exec_vmread32 and exec_vmwrite32 functions to access 32-bit fields in VMCS; Update related variables type for vmread/vmwrite operations; Update related caller according to VMCS fields size. V1--V2: This is new part of this patch serial to only update 32 bit vmread/vmread opertions and related caller. V2-->V3: Update related variables type in data structure for exec_vmread32/exec_vmwrite32. Rename temp variable 'low' into 'value' for exec_vmread32; V3-->V4: Remove useless type conversion. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-16 15:43:25 +08:00
uint32_t ia32_sysenter_cs;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
uint64_t ia32_sysenter_esp;
uint64_t ia32_sysenter_eip;
uint64_t ia32_debugctl;
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
uint64_t dr7;
uint64_t tsc_offset;
trusty: init & switch world fix - when init, cr0 & cr4 should read from VMCS - when world switch, cr0/cr4 read shadow should also be save/restore v2: - use context->vmx_cr0/cr4 to save/restore VMX_GUEST_CR0/CR4 - use context->cr0/cr4 to save/restore VMX_CR0/CR4_READ_SHADOW Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-16 14:46:51 +08:00
uint64_t vmx_cr0;
uint64_t vmx_cr4;
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
uint64_t vmx_cr0_read_shadow;
uint64_t vmx_cr4_read_shadow;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* The 512 bytes area to save the FPU/MMX/SSE states for the guest */
uint64_t
fxstore_guest_area[VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE / sizeof(uint64_t)]
__aligned(16);
};
/* 2 worlds: 0 for Normal World, 1 for Secure World */
#define NR_WORLD 2
#define NORMAL_WORLD 0
#define SECURE_WORLD 1
apicv: cancel event injection if vcpu is scheduled out And re-inject the event after vcpu is scheduled in. Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2018-02-28 19:33:13 +08:00
struct event_injection_info {
uint32_t intr_info;
uint32_t error_code;
};
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
struct cpu_context {
struct run_context run_ctx;
struct ext_context ext_ctx;
};
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
struct vcpu_arch {
int cur_context;
vcpu: add ext context support for world switch move most of fields from run_context into ext_context for world switch. these fields do not need doing runtime save/restore during vm exit/entry. v3: - update cr0/cr4 registers switch method v2: - use struct name ext_context instead of saved_context - updated according to previous v2 patch Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-29 16:05:37 +08:00
struct cpu_context contexts[NR_WORLD];
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* A pointer to the VMCS for this CPU. */
void *vmcs;
HV:treewide:Add 16-bit atomic operations and update vpid type There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 11:09:10 +08:00
uint16_t vpid;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* Holds the information needed for IRQ/exception handling. */
struct {
/* The number of the exception to raise. */
irq: convert irq/vector numbers to unsigned Currently irq and vector numbers are used inconsistently. * Sometimes vector or irq ids is used in bit operations, indicating that they should be unsigned (which is required by MISRA C). * At the same time we use -1 to indicate an unknown irq (in common_register_handler()) or unavailable irq (in alloc_irq()). Also (irq < 0) or (vector < 0) are used for error checking. These indicate that irq or vector ids should be signed. This patch converts irq and vector numbers to unsigned 32-bit integers, and replace the previous -1 with IRQ_INVALID or VECTOR_INVALID. The branch conditions are updated accordingly. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-08 20:53:59 +08:00
uint32_t exception;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* The error number for the exception. */
HV: handle integral issue report by MISRA-C The main focus on: constant suffix U/UL; parameters cast like uint32 to a uint16 variable; unify some APIs interface, consist with the callers. also modify some places to unify code style Signed-off-by: Minggui Cao <minggui.cao@intel.com>
2018-07-12 11:47:49 +08:00
uint32_t error;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
} exception_info;
uint8_t lapic_mask;
uint32_t irq_window_enabled;
uint32_t nrexits;
/* Auxiliary TSC value */
uint64_t msr_tsc_aux;
/* VCPU context state information */
revise type of 'exit_reason' and 'inst_len' in vcpu_arch SDM 24.9.1 Volume3: - 'Exit reason' field in VMCS is 32 bits. SDM 24.9.4 in Volume3 - 'VM-exit instruction length' field in VMCS is 32 bits. This patch is to redefine the data types of above fields in 'struct vcpu_arch' and udpate the code using these two fields. Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-04-16 23:15:31 +08:00
uint32_t exit_reason;
check validity of 'VM-exit Int-Info' before extracting vector 1. exception vector and other information can be extracted from 'VM-Exit Interrupt-Information' field of VMCS only if bit31 (Valid) is set. -Intel SDM 24.9.2, Vol3 2. Rename 'exit-interrupt_info' to 'idt_vectoring_info' in 'struct vcpu_arch', which is consistent with SDM 24.9.3, Vol3 3. 'IDT-vectoring information' in VMCS is 32bit -Intel SDM 24.9.3, Vol3 Update the type of 'idt_vectoring_info' in 'struct vcpu_arch'from 'uint32_t' to 'uint64_t'. Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-04-17 21:11:54 +08:00
uint32_t idt_vectoring_info;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
uint64_t exit_qualification;
revise type of 'exit_reason' and 'inst_len' in vcpu_arch SDM 24.9.1 Volume3: - 'Exit reason' field in VMCS is 32 bits. SDM 24.9.4 in Volume3 - 'VM-exit instruction length' field in VMCS is 32 bits. This patch is to redefine the data types of above fields in 'struct vcpu_arch' and udpate the code using these two fields. Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-04-16 23:15:31 +08:00
uint32_t inst_len;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* Information related to secondary / AP VCPU start-up */
HV: vlapic: minimize explicit casts by adjusting types To minimize explicit casts, this patch adjusts the types of function parameters and structure fields related to vlapic and update the types in the internal implementation accordingly. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 17:11:27 +08:00
enum vm_cpu_mode cpu_mode;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
uint8_t nr_sipi;
uint32_t sipi_vector;
/* interrupt injection information */
replace pending_intr with pending_req the pending_intr is not only serving for interrupt but also for different request including TLB & TMR updating, so change the function & variants name accordingly. Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-25 12:29:00 +08:00
uint64_t pending_req;
apicv: cancel event injection if vcpu is scheduled out And re-inject the event after vcpu is scheduled in. Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2018-02-28 19:33:13 +08:00
bool inject_event_pending;
struct event_injection_info inject_info;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* per vcpu lapic */
void *vlapic;
};
struct vm;
struct vcpu {
HV:Treewide:Update the type of vcpu id as uint16_t In the hypervisor, virtual cpu id is defined as "int" or "uint32_t" type in the hypervisor. So there are some sign conversion issues about virtual cpu id (vcpu_id) reported by static analysis tool. Sign conversion violates the rules of MISRA C:2012. BTW, virtual cpu id has different names (vcpu_id, cpu_id, logical_id) for different modules of HV, its type is defined as "int" or "uint32_t" in the HV. cpu_id type and logical_id type clean up will be done in other patchs. V1-->V2: More clean up the type of vcpu id; "%hu" is for vcpu id in the print function. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-03 16:41:54 +08:00
uint16_t pcpu_id; /* Physical CPU ID of this VCPU */
uint16_t vcpu_id; /* virtual identifier for VCPU */
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
struct vcpu_arch arch_vcpu;
/* Architecture specific definitions for this VCPU */
struct vm *vm; /* Reference to the VM this VCPU belongs to */
void *entry_addr; /* Entry address for this VCPU when first started */
/* State of this VCPU before suspend */
volatile enum vcpu_state prev_state;
volatile enum vcpu_state state; /* State of this VCPU */
/* State of debug request for this VCPU */
volatile enum vcpu_state dbg_req_state;
HV:treewide:transfer the struct member types to non-basic types The struct member types should be transfer to non-basic types, chaned it to length-prefix(uint32_t,int32_t ...) type. Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 14:29:34 +08:00
uint64_t sync; /*hold the bit events*/
HV:treewide:rename struct vlapic as struct acrn_vlapic There are many naming violations detected by static analysis tool. Data structure type name is the same as variable name. According to naming convention rules, If the data structure type is used by multi modules and its name meaning is simplistic (such as vcpu, vm), its name needs prefix "acrn_". Rename struct vlapic as struct acrn_vlapic Replace regular expression:s/struct vlapic\([ ),;\t\*]\+\)/struct acrn_vlapic\1 Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 14:46:26 +08:00
struct acrn_vlapic *vlapic; /* per vCPU virtualized LAPIC */
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
struct list_head run_list; /* inserted to schedule runqueue */
HV:treewide:transfer the struct member types to non-basic types The struct member types should be transfer to non-basic types, chaned it to length-prefix(uint32_t,int32_t ...) type. Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 14:29:34 +08:00
uint64_t pending_pre_work; /* any pre work pending? */
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
bool launched; /* Whether the vcpu is launched on target pcpu */
HV:treewide:transfer the struct member types to non-basic types The struct member types should be transfer to non-basic types, chaned it to length-prefix(uint32_t,int32_t ...) type. Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 14:29:34 +08:00
uint32_t paused_cnt; /* how many times vcpu is paused */
HV:treewide:Update the type of return value and parameters of atomic operations There are many type conversions in the atomic operations invoking reported by static analysis tool. These type conversions voilate MISRA C. To keep uniform naming convention, rename atomic operation function names: atomic_set_int/long --> atomic_set32/64; atomic_clear_int/long --> atomic_clear32/64; atomic_load --> atomic_load32; atomic_store --> atomic_store32; atomic_swap --> atomic_swap32; atomic_readandclear --> atomic_readandclear32; atomic_inc --> atomic_inc32; atomic_dec --> atomic_dec32; atomic_cmpxchg --> atomic_cmpxchg32; atomic_xadd --> atomic_xadd32. Update the type of atomic_load32/64, atomic_store32/64, atomic_swap32/64, atomic_cmpxchg32/6. Update related variables and callers. Note: the type of return value and parameters of atomic_xadd32/64 still keep signed int/long since caller pass negative variable to atomic_xadd32/64; V1-->V2: Add comments for atomic_set/clear to differ from bitmap_set/clear. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie.Mao <junjie.mao@intel.com>
2018-07-18 13:36:41 +08:00
uint32_t running; /* vcpu is picked up and run? */
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
HV: io: unify vhm_request req and mem_io in vcpu The current struct vcpu has two members, namely 'struct vhm_request req' and 'struct mem_io mmio', that hold similar info, including the address, direction, size, value and status of mmio reqeusts. As a step towards a unified framework for both MMIO/PIO, this patch unifies these two members by a tailored version of vhm_reqeust, mostly with the reserved fields dropped. The definitions to request types, directions and process status are reused. Handling errors during emulations will be revisited after the I/O emulation paths are unified. Thus for this patch the mmio.mmio_status in inherited by io_req.processed which is not yet properly processed. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-24 19:05:47 +08:00
struct io_request req; /* used by io/ept emulation */
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* save guest msr tsc aux register.
* Before VMENTRY, save guest MSR_TSC_AUX to this fields.
* After VMEXIT, restore this fields to guest MSR_TSC_AUX.
* This is only temperary workaround. Once MSR emulation
* is enabled, we should remove this fields and related
* code.
*/
uint64_t msr_tsc_aux_guest;
hv: code clean up regarding to guest_msrs Change guest_msrs in vcpu data structure from pointer to array, which could avoid the dynamic memory allocation. v1 -> v2: * Remove the unnecessary initialization for guest_msrs[] since vcpu is allocated by calloc. Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-24 16:21:59 +08:00
uint64_t guest_msrs[IDX_MAX_MSR];
hv: basic MTRR virtualization Linux commit edfe63ec97ed ("x86/mtrr: Fix Xorg crashes in Qemu sessions") disables PAT feature if MTRR is not enabled. This patch does partial emulation of MTRR to prevent this from happening: enable fixed-range MTRRs and disable virable range MTRRs By default IA32_PAT MSR (SDM Vol3 11.12.4, Table 11-12) doesn't include 'WC' type. If MTRR is disabled from the guests, Linux doesn't allow writing IA32_PAT MSR so WC type can't be enabled. This creates some performance issues for certian applications that rely on WC memory type. Implementation summary: - Enable MTRR feature: MTRRdefType.E=1 - Enable fixed range MTRRs: MTRRCAP.fix=1, MTRRdefType.FE=1 - For simplicity, disable variable range MTRRs: MTRRCAP.vcnt=0. It's expected that this bit is honored by the guests and they won't change the guest memory type through variable MTRRs. Signed-off-by: bliu11 <baohong.liu@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-30 08:41:52 +08:00
#ifdef CONFIG_MTRR_ENABLED
struct mtrr_state mtrr;
#endif
vcpu: add get/set register APIs there will be 3 types of vcpu runtime contexts: - runtime contexts always saved/restored during VM exit/entry, which include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and msr for spectre control (ia32_spec_ctrl) - runtime contexts on-demand cached/updated during VM exit/entry, which include frequently used registers rsp, rip, efer, rflags, cr0 and cr4 - runtime contexts always read/write from/to VMCS, which include left registers not in above this patch add get/set register APIs for vcpu runtime contexts, and unified the save/restore method for them according to above description. v3: - update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4, use on-demand cache for reading, but always write to VMCS for writing. v2: - use reg_cached/reg_updated for on-demand runtime contexts - always read/write cr3 from/to VMCS Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 14:56:47 +08:00
uint64_t reg_cached;
uint64_t reg_updated;
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
};
dump vcpu registers on correct vcpu after updated cpu context get/set method, the vcpu_dumreg cmd is not correct anymore as the registers may read from VMCS but meantime hv shell may not be running on target vcpu. this patch take use of smp_call_function for vcpu dumpreg and make the dump always come from correct vcpu. v2: - use str pointer to get vcpu_dumpreg context instead of print out directly in notify handler. Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-08 11:43:06 +08:00
struct vcpu_dump {
struct vcpu *vcpu;
char *str;
int str_max;
};
hv:Replace 0(cpu_id) with BOOT_CPU_ID Replace 0(pcpu_id/vcpu_id) with BOOT_CPU_ID Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 15:17:41 +08:00
#define is_vcpu_bsp(vcpu) ((vcpu)->vcpu_id == BOOT_CPU_ID)
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* do not update Guest RIP for next VM Enter */
HV: Avoiding assignment opperation inside macro To follow the Misra-c standard, the assignment operation inside function-like macro should be avoided. Replaced the violations macro using inline function instead. Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2018-06-23 06:44:48 +08:00
static inline void vcpu_retain_rip(struct vcpu *vcpu)
{
HV: code cleanup as MISRA-C report for guest/vmsr like: constant of unsigned int need add U/UL as surfix. enum value can't use to give or compare with int directlly. unsigned and signed mis-matched Signed-off-by: Minggui Cao <minggui.cao@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-10 19:07:46 +08:00
(vcpu)->arch_vcpu.inst_len = 0U;
HV: Avoiding assignment opperation inside macro To follow the Misra-c standard, the assignment operation inside function-like macro should be avoided. Replaced the violations macro using inline function instead. Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2018-06-23 06:44:48 +08:00
}
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
/* External Interfaces */
vcpu: add get/set register APIs there will be 3 types of vcpu runtime contexts: - runtime contexts always saved/restored during VM exit/entry, which include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and msr for spectre control (ia32_spec_ctrl) - runtime contexts on-demand cached/updated during VM exit/entry, which include frequently used registers rsp, rip, efer, rflags, cr0 and cr4 - runtime contexts always read/write from/to VMCS, which include left registers not in above this patch add get/set register APIs for vcpu runtime contexts, and unified the save/restore method for them according to above description. v3: - update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4, use on-demand cache for reading, but always write to VMCS for writing. v2: - use reg_cached/reg_updated for on-demand runtime contexts - always read/write cr3 from/to VMCS Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 14:56:47 +08:00
uint64_t vcpu_get_gpreg(struct vcpu *vcpu, uint32_t reg);
void vcpu_set_gpreg(struct vcpu *vcpu, uint32_t reg, uint64_t val);
uint64_t vcpu_get_rip(struct vcpu *vcpu);
void vcpu_set_rip(struct vcpu *vcpu, uint64_t val);
uint64_t vcpu_get_rsp(struct vcpu *vcpu);
void vcpu_set_rsp(struct vcpu *vcpu, uint64_t val);
uint64_t vcpu_get_efer(struct vcpu *vcpu);
void vcpu_set_efer(struct vcpu *vcpu, uint64_t val);
uint64_t vcpu_get_rflags(struct vcpu *vcpu);
void vcpu_set_rflags(struct vcpu *vcpu, uint64_t val);
uint64_t vcpu_get_cr0(struct vcpu *vcpu);
hv:Changed several APIs to void type Since these APIs always return 0, change them to void type, vcpu_set_cr0() vmx_write_cr0() vcpu_set_cr4() vmx_write_cr4() kick_notification() tsc_deadline_handler() dmar_fault_handler() ptdev_interrupt_handler() Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-22 11:12:37 +08:00
void vcpu_set_cr0(struct vcpu *vcpu, uint64_t val);
vcpu: add get/set register APIs there will be 3 types of vcpu runtime contexts: - runtime contexts always saved/restored during VM exit/entry, which include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and msr for spectre control (ia32_spec_ctrl) - runtime contexts on-demand cached/updated during VM exit/entry, which include frequently used registers rsp, rip, efer, rflags, cr0 and cr4 - runtime contexts always read/write from/to VMCS, which include left registers not in above this patch add get/set register APIs for vcpu runtime contexts, and unified the save/restore method for them according to above description. v3: - update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4, use on-demand cache for reading, but always write to VMCS for writing. v2: - use reg_cached/reg_updated for on-demand runtime contexts - always read/write cr3 from/to VMCS Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 14:56:47 +08:00
uint64_t vcpu_get_cr2(struct vcpu *vcpu);
void vcpu_set_cr2(struct vcpu *vcpu, uint64_t val);
uint64_t vcpu_get_cr4(struct vcpu *vcpu);
hv:Changed several APIs to void type Since these APIs always return 0, change them to void type, vcpu_set_cr0() vmx_write_cr0() vcpu_set_cr4() vmx_write_cr4() kick_notification() tsc_deadline_handler() dmar_fault_handler() ptdev_interrupt_handler() Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-22 11:12:37 +08:00
void vcpu_set_cr4(struct vcpu *vcpu, uint64_t val);
vcpu: add get/set register APIs there will be 3 types of vcpu runtime contexts: - runtime contexts always saved/restored during VM exit/entry, which include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and msr for spectre control (ia32_spec_ctrl) - runtime contexts on-demand cached/updated during VM exit/entry, which include frequently used registers rsp, rip, efer, rflags, cr0 and cr4 - runtime contexts always read/write from/to VMCS, which include left registers not in above this patch add get/set register APIs for vcpu runtime contexts, and unified the save/restore method for them according to above description. v3: - update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4, use on-demand cache for reading, but always write to VMCS for writing. v2: - use reg_cached/reg_updated for on-demand runtime contexts - always read/write cr3 from/to VMCS Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 14:56:47 +08:00
uint64_t vcpu_get_pat_ext(struct vcpu *vcpu);
void vcpu_set_pat_ext(struct vcpu *vcpu, uint64_t val);
HV: treewide: enforce unsignedness of pcpu_id In the hypervisor, physical cpu id is defined as "int" or "uint32_t" type in the hypervisor. So there are some sign conversion issues about physical cpu id (pcpu_id) reported by static analysis tool. Sign conversion violates the rules of MISRA C:2012. In this patch, define physical cpu id as "uint16_t" type for all modules in the hypervisor and change related codes. The valid range of pcpu_id is 0~65534, INVALID_PCPU_ID is defined to the invalid pcpu_id for error detection, BROADCAST_PCPU_ID is broadcast pcpu_id used to notify all valid pcpu. The type of pcpu_id in the struct vcpu and vcpu_id is "int" type, this will be fixed in another patch. V1-->V2: * Change the type of pcpu_id from uint32_t to uint16_t; * Define INVALID_PCPU_ID for error detection; * Define BROADCAST_PCPU_ID to notify all valid pcpu. V2-->V3: * Update comments for INVALID_PCPU_ID and BROADCAST_PCPU_ID; * Update addtional pcpu_id; * Convert hexadecimals to unsigned to meet the type of pcpu_id; * Clean up for MIN_PCPU_ID and MAX_PCPU_ID, they will be defined by configuration. Note: fix bug in the init_lapic(), the pcpu_id shall be less than 8, this is constraint by implement in the init_lapic(). Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-20 15:42:52 +08:00
struct vcpu* get_ever_run_vcpu(uint16_t pcpu_id);
HV:treewide:Update cpu_id type as uint_16 There are extra type conversion in the HV since cpu_id type is uint32_t and the return value type of get_cpu_id is uint16_t. BTW, the name of cpu_id is not clear enough to express its usage. So the following updates are made in this patch: Update cpu_id type as unit_16 to reduce type casting; Update related temporary variables type; Update related print argument; Change the input parameter name of interrupt_init as cpu_id to keep align with function implement; Rename cpu_id as pcpu_id as needed. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-04 10:37:43 +08:00
int create_vcpu(uint16_t pcpu_id, struct vm *vm, struct vcpu **rtn_vcpu_handle);
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
int start_vcpu(struct vcpu *vcpu);
int shutdown_vcpu(struct vcpu *vcpu);
fix parted of "missing for discarded return value" MISRA C required that return value should be used, missing for it should add "(void)" prefix before the function call. Some function can be declared without return value to avoid this problem. Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-19 10:15:48 +08:00
void destroy_vcpu(struct vcpu *vcpu);
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
void reset_vcpu(struct vcpu *vcpu);
void pause_vcpu(struct vcpu *vcpu, enum vcpu_state new_state);
void resume_vcpu(struct vcpu *vcpu);
void schedule_vcpu(struct vcpu *vcpu);
HV: treewide: enforce unsignedness of pcpu_id In the hypervisor, physical cpu id is defined as "int" or "uint32_t" type in the hypervisor. So there are some sign conversion issues about physical cpu id (pcpu_id) reported by static analysis tool. Sign conversion violates the rules of MISRA C:2012. In this patch, define physical cpu id as "uint16_t" type for all modules in the hypervisor and change related codes. The valid range of pcpu_id is 0~65534, INVALID_PCPU_ID is defined to the invalid pcpu_id for error detection, BROADCAST_PCPU_ID is broadcast pcpu_id used to notify all valid pcpu. The type of pcpu_id in the struct vcpu and vcpu_id is "int" type, this will be fixed in another patch. V1-->V2: * Change the type of pcpu_id from uint32_t to uint16_t; * Define INVALID_PCPU_ID for error detection; * Define BROADCAST_PCPU_ID to notify all valid pcpu. V2-->V3: * Update comments for INVALID_PCPU_ID and BROADCAST_PCPU_ID; * Update addtional pcpu_id; * Convert hexadecimals to unsigned to meet the type of pcpu_id; * Clean up for MIN_PCPU_ID and MAX_PCPU_ID, they will be defined by configuration. Note: fix bug in the init_lapic(), the pcpu_id shall be less than 8, this is constraint by implement in the init_lapic(). Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-20 15:42:52 +08:00
int prepare_vcpu(struct vm *vm, uint16_t pcpu_id);
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
HV:treewide:Cleanup the type for parameters of bitmap operations For reducing sign conversion in hypervisor: Update parameters of bitmap operations as unsigned type; Update the input of related caller as unsigned type when the caller's input parameter is const variable or the variable is only used by bitmap operations. V1-->V2: (1) Explicit casting for the first parameter of all bitmap operations; (2) Remove mask operation for explicit casting of all bitmap operations, since masking is useless. Otherwise, this trucation is dangerous. V2-->V3: (1) Explicit casting for all bitmap operations parameter; (2) Masking bit offset with 6-bit; (3) Add few comments about bit offset. V3-->V4: add '\' for some statement of bitmap macro Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-30 00:17:34 +08:00
void request_vcpu_pre_work(struct vcpu *vcpu, uint16_t pre_work_id);
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
dump vcpu registers on correct vcpu after updated cpu context get/set method, the vcpu_dumreg cmd is not correct anymore as the registers may read from VMCS but meantime hv shell may not be running on target vcpu. this patch take use of smp_call_function for vcpu dumpreg and make the dump always come from correct vcpu. v2: - use str pointer to get vcpu_dumpreg context instead of print out directly in notify handler. Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-08 11:43:06 +08:00
void vcpu_dumpreg(void *data);
initial import internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 20:57:14 +08:00
#endif
#endif