2018-03-07 20:57:14 +08:00
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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2018-05-26 01:49:13 +08:00
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* SPDX-License-Identifier: BSD-3-Clause
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2018-03-07 20:57:14 +08:00
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*/
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2018-05-22 08:30:50 +08:00
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#include <hypervisor.h>
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2018-03-07 20:57:14 +08:00
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#include "uart16550.h"
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#if defined(CONFIG_SERIAL_PIO_BASE)
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2018-07-30 11:29:34 +08:00
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static bool serial_port_mapped = true;
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static bool uart_enabled = true;
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2018-03-07 20:57:14 +08:00
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#define UART_BASE_ADDRESS CONFIG_SERIAL_PIO_BASE
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#elif defined(CONFIG_SERIAL_MMIO_BASE)
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2018-07-30 11:29:34 +08:00
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static bool serial_port_mapped;
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static bool uart_enabled = true;
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2018-03-07 20:57:14 +08:00
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#define UART_BASE_ADDRESS CONFIG_SERIAL_MMIO_BASE
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#else
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#warning "no uart base configure, please check!"
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2018-07-30 11:29:34 +08:00
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static bool serial_port_mapped;
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static bool uart_enabled;
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#define UART_BASE_ADDRESS 0UL
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2018-03-07 20:57:14 +08:00
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#endif
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typedef uint32_t uart_reg_t;
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2018-07-27 16:23:09 +08:00
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static uint64_t uart_base_address;
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2018-03-07 20:57:14 +08:00
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2018-07-27 16:23:09 +08:00
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static spinlock_t uart_rx_lock;
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static spinlock_t uart_tx_lock;
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2018-03-07 20:57:14 +08:00
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2018-07-30 11:29:34 +08:00
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/**
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* @pre uart_enabled == true
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*/
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static inline uint32_t uart16550_read_reg(uint64_t base, uint16_t reg_idx)
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2018-03-07 20:57:14 +08:00
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{
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2018-07-30 11:29:34 +08:00
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if (serial_port_mapped) {
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2018-08-01 18:19:08 +08:00
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return pio_read8((uint16_t)base + reg_idx);
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2018-03-07 20:57:14 +08:00
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} else {
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2018-09-06 13:50:10 +08:00
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return mmio_read32((void *)((uint32_t *)hpa2hva(base) +
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reg_idx));
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2018-03-07 20:57:14 +08:00
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}
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}
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2018-07-30 11:29:34 +08:00
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/**
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* @pre uart_enabled == true
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*/
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2018-04-13 14:51:25 +08:00
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static inline void uart16550_write_reg(uint64_t base,
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2018-07-30 11:29:34 +08:00
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uint32_t val, uint16_t reg_idx)
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2018-03-07 20:57:14 +08:00
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{
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2018-07-30 11:29:34 +08:00
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if (serial_port_mapped) {
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2018-08-01 18:19:08 +08:00
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pio_write8((uint8_t)val, (uint16_t)base + reg_idx);
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2018-03-07 20:57:14 +08:00
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} else {
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2018-09-06 13:50:10 +08:00
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mmio_write32(val, (void *)((uint32_t *)hpa2hva(base) +
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reg_idx));
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2018-03-07 20:57:14 +08:00
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}
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}
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2018-07-27 16:23:09 +08:00
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static void uart16550_calc_baud_div(uint32_t ref_freq,
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uint32_t *baud_div_ptr, uint32_t baud_rate_arg)
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2018-03-07 20:57:14 +08:00
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{
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2018-07-25 11:19:52 +08:00
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uint32_t baud_rate = baud_rate_arg;
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2018-07-30 11:29:34 +08:00
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uint32_t baud_multiplier = baud_rate < BAUD_460800 ? 16U : 13U;
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2018-03-07 20:57:14 +08:00
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2018-07-30 11:29:34 +08:00
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if (baud_rate == 0U) {
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2018-06-15 09:49:15 +08:00
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baud_rate = BAUD_115200;
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2018-07-13 06:02:55 +08:00
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}
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2018-03-07 20:57:14 +08:00
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*baud_div_ptr = ref_freq / (baud_multiplier * baud_rate);
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}
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2018-07-30 11:29:34 +08:00
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/**
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* @pre uart_enabled == true
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*/
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2018-07-27 16:23:09 +08:00
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static void uart16550_set_baud_rate(uint32_t baud_rate)
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2018-03-07 20:57:14 +08:00
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{
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2018-07-27 16:23:09 +08:00
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uint32_t baud_div, duart_clock = UART_CLOCK_RATE;
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2018-03-07 20:57:14 +08:00
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uart_reg_t temp_reg;
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/* Calculate baud divisor */
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2018-07-27 16:23:09 +08:00
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uart16550_calc_baud_div(duart_clock, &baud_div, baud_rate);
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2018-03-07 20:57:14 +08:00
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2018-07-12 11:59:19 +08:00
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/* Enable DLL and DLM registers for setting the Divisor */
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2018-07-27 16:23:09 +08:00
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temp_reg = uart16550_read_reg(uart_base_address, UART16550_LCR);
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2018-07-12 11:59:19 +08:00
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temp_reg |= LCR_DLAB;
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2018-07-27 16:23:09 +08:00
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uart16550_write_reg(uart_base_address, temp_reg, UART16550_LCR);
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2018-03-07 20:57:14 +08:00
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2018-07-12 11:59:19 +08:00
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/* Write the appropriate divisor value */
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2018-07-27 16:23:09 +08:00
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uart16550_write_reg(uart_base_address,
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2018-07-30 11:29:34 +08:00
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((baud_div >> 8U) & 0xFFU), UART16550_DLM);
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2018-07-27 16:23:09 +08:00
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uart16550_write_reg(uart_base_address,
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(baud_div & 0xFFU), UART16550_DLL);
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2018-03-07 20:57:14 +08:00
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2018-07-12 11:59:19 +08:00
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/* Disable DLL and DLM registers */
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temp_reg &= ~LCR_DLAB;
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2018-07-27 16:23:09 +08:00
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uart16550_write_reg(uart_base_address, temp_reg, UART16550_LCR);
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2018-03-07 20:57:14 +08:00
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}
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2018-07-27 16:23:09 +08:00
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void uart16550_init(void)
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2018-03-07 20:57:14 +08:00
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{
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2018-07-30 11:29:34 +08:00
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if (!uart_enabled) {
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return;
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}
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if (uart_base_address == 0UL) {
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2018-07-27 16:23:09 +08:00
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uart_base_address = UART_BASE_ADDRESS;
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2018-03-07 20:57:14 +08:00
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}
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2018-07-27 16:23:09 +08:00
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spinlock_init(&uart_rx_lock);
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spinlock_init(&uart_tx_lock);
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/* Enable TX and RX FIFOs */
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uart16550_write_reg(uart_base_address,
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FCR_FIFOE | FCR_RFR | FCR_TFR, UART16550_FCR);
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/* Set-up data bits / parity / stop bits. */
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uart16550_write_reg(uart_base_address,
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(LCR_WL8 | LCR_NB_STOP_BITS_1 | LCR_PARITY_NONE),
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UART16550_LCR);
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/* Disable interrupts (we use polling) */
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uart16550_write_reg(uart_base_address,
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UART_IER_DISABLE_ALL, UART16550_IER);
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/* Set baud rate */
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uart16550_set_baud_rate(BAUD_115200);
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/* Data terminal ready + Request to send */
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uart16550_write_reg(uart_base_address,
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MCR_RTS | MCR_DTR, UART16550_MCR);
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2018-03-07 20:57:14 +08:00
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}
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2018-07-27 16:23:09 +08:00
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char uart16550_getc(void)
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2018-03-07 20:57:14 +08:00
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{
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2018-07-27 16:23:09 +08:00
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char ret = -1;
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2018-03-07 20:57:14 +08:00
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2018-07-30 11:29:34 +08:00
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if (!uart_enabled) {
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return ret;
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}
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2018-07-27 16:23:09 +08:00
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spinlock_obtain(&uart_rx_lock);
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2018-03-07 20:57:14 +08:00
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/* If a character has been received, read it */
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2018-07-27 16:23:09 +08:00
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if ((uart16550_read_reg(uart_base_address, UART16550_LSR) & LSR_DR)
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2018-03-07 20:57:14 +08:00
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== LSR_DR) {
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/* Read a character */
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2018-07-27 16:23:09 +08:00
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ret = uart16550_read_reg(uart_base_address, UART16550_RBR);
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2018-03-07 20:57:14 +08:00
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}
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2018-07-27 16:23:09 +08:00
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spinlock_release(&uart_rx_lock);
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return ret;
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2018-03-07 20:57:14 +08:00
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}
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2018-07-30 11:29:34 +08:00
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/**
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* @pre uart_enabled == true
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*/
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2018-09-17 13:39:40 +08:00
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static void uart16550_putc(char c)
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2018-03-07 20:57:14 +08:00
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{
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2018-09-17 13:39:40 +08:00
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uint8_t temp;
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2018-07-27 16:23:09 +08:00
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uint32_t reg;
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2018-09-17 13:39:40 +08:00
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2018-03-07 20:57:14 +08:00
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/* Ensure there are no further Transmit buffer write requests */
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do {
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2018-07-27 16:23:09 +08:00
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reg = uart16550_read_reg(uart_base_address, UART16550_LSR);
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} while ((reg & LSR_THRE) == 0U || (reg & LSR_TEMT) == 0U);
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2018-03-07 20:57:14 +08:00
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2018-09-17 13:39:40 +08:00
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temp = (uint8_t)c;
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2018-03-07 20:57:14 +08:00
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/* Transmit the character. */
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2018-09-17 13:39:40 +08:00
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uart16550_write_reg(uart_base_address, (uint32_t)temp, UART16550_THR);
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2018-03-07 20:57:14 +08:00
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}
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2018-09-18 17:50:26 +08:00
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size_t uart16550_puts(const char *buf, uint32_t len)
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2018-03-07 20:57:14 +08:00
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{
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2018-07-27 16:23:09 +08:00
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uint32_t i;
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2018-07-30 11:29:34 +08:00
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if (!uart_enabled) {
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2018-09-18 17:50:26 +08:00
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return len;
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2018-07-30 11:29:34 +08:00
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}
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2018-07-27 16:23:09 +08:00
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spinlock_obtain(&uart_tx_lock);
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for (i = 0U; i < len; i++) {
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/* Transmit character */
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2018-07-30 11:29:34 +08:00
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uart16550_putc(*buf);
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2018-07-27 16:23:09 +08:00
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if (*buf == '\n') {
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/* Append '\r', no need change the len */
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2018-07-30 11:29:34 +08:00
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uart16550_putc('\r');
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2018-07-27 16:23:09 +08:00
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}
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buf++;
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2018-03-07 20:57:14 +08:00
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}
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2018-07-27 16:23:09 +08:00
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spinlock_release(&uart_tx_lock);
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2018-09-18 17:50:26 +08:00
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return len;
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2018-07-27 16:23:09 +08:00
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}
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2018-03-07 20:57:14 +08:00
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2018-07-30 11:29:34 +08:00
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void uart16550_set_property(bool enabled, bool port_mapped, uint64_t base_addr)
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2018-03-07 20:57:14 +08:00
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{
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uart_enabled = enabled;
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serial_port_mapped = port_mapped;
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2018-07-27 16:23:09 +08:00
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uart_base_address = base_addr;
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2018-03-07 20:57:14 +08:00
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}
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